Lines Matching refs:OpWidth
172 #define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, \ argument
179 DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \
184 AMDGPUDisassembler::OpWidthTy OpWidth, in decodeSrcOp() argument
191 return addOperand(Inst, DAsm->decodeSrcOp(OpWidth, EncImm, MandatoryLiteral, in decodeSrcOp()
197 #define DECODE_OPERAND_REG_7(RegClass, OpWidth) \ argument
198 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)
204 template <AMDGPUDisassembler::OpWidthTy OpWidth>
207 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm | AMDGPU::EncValues::IS_VGPR, in decodeAV10()
212 template <AMDGPUDisassembler::OpWidthTy OpWidth>
216 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, 0, in decodeSrcReg9()
223 template <AMDGPUDisassembler::OpWidthTy OpWidth>
226 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, 0, in decodeSrcA9()
232 template <AMDGPUDisassembler::OpWidthTy OpWidth>
236 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm, false, 0, in decodeSrcAV10()
245 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
250 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, ImmWidth, in decodeSrcRegOrImm9()
256 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
261 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, ImmWidth, in decodeSrcRegOrImmA9()
265 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
270 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, true, ImmWidth, in decodeSrcRegOrImmDeferred9()