107   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);  in decodeSOPPBrTarget()  local
114   if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0))  in decodeSOPPBrTarget()
121   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);  in decodeSMEMOffset()  local
123   if (DAsm->isGFX12Plus()) { // GFX12 supports 24-bit signed offsets.  in decodeSMEMOffset()
125   } else if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets.  in decodeSMEMOffset()
135   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);  in decodeBoolReg()  local
136   return addOperand(Inst, DAsm->decodeBoolReg(Val));  in decodeBoolReg()
142   auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);  in decodeSplitBarrier()  local
143   return addOperand(Inst, DAsm->decodeSplitBarrier(Val));  in decodeSplitBarrier()
148   auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);  in decodeDpp8FI()  local
149   return addOperand(Inst, DAsm->decodeDpp8FI(Val));  in decodeDpp8FI()
156     auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
157     return addOperand(Inst, DAsm->DecoderName(Imm));                           \
167     auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
169         Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm));      \
177     auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
179                       DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm,   \
190   auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);  in decodeSrcOp()  local
191   return addOperand(Inst, DAsm->decodeSrcOp(OpWidth, EncImm, MandatoryLiteral,  in decodeSrcOp()
316   auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);  in DECODE_OPERAND_REG_8()  local
317   return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));  in DECODE_OPERAND_REG_8()
327   auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);  in DecodeVGPR_16_Lo128RegisterClass()  local
328   return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));  in DecodeVGPR_16_Lo128RegisterClass()
336   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);  in decodeOperand_VSrcT16_Lo128()  local
341     return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));  in decodeOperand_VSrcT16_Lo128()
343   return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16,  in decodeOperand_VSrcT16_Lo128()
352   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);  in decodeOperand_VSrcT16()  local
357     return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));  in decodeOperand_VSrcT16()
359   return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16,  in decodeOperand_VSrcT16()
366   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);  in decodeOperand_KImmFP()  local
367   return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));  in decodeOperand_KImmFP()
372   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);  in decodeOperandVOPDDstY()  local
373   return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val));  in decodeOperandVOPDDstY()
393   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);  in decodeAVLdSt()  local
394   if (!DAsm->isGFX90A()) {  in decodeAVLdSt()
403     uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags;  in decodeAVLdSt()
406     const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo();  in decodeAVLdSt()
421   return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256));  in decodeAVLdSt()
435   auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);  in decodeOperand_VSrc_f64()  local
437                     DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64,  in decodeOperand_VSrc_f64()
451   auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);  in DECODE_SDWA()  local
452   return addOperand(Inst, DAsm->decodeVersionImm(Imm));  in DECODE_SDWA()