Lines Matching refs:AMDGPU
43 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
44 : AMDGPU::EncValues::SGPR_MAX_SI)
50 if (!STI.hasFeature(AMDGPU::FeatureWavefrontSize64) && in addDefaultWaveSize()
51 !STI.hasFeature(AMDGPU::FeatureWavefrontSize32)) { in addDefaultWaveSize()
56 STICopy.ToggleFeature(AMDGPU::FeatureWavefrontSize32); in addDefaultWaveSize()
68 CodeObjectVersion(AMDGPU::getDefaultAMDHSACodeObjectVersion()) { in AMDGPUDisassembler()
70 if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus()) in AMDGPUDisassembler()
73 for (auto [Symbol, Code] : AMDGPU::UCVersion::getGFXVersions()) in AMDGPUDisassembler()
82 CodeObjectVersion = AMDGPU::getAMDHSACodeObjectVersion(Version); in setABIVersion()
95 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); in insertNamedMCOperand()
169 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \
187 AMDGPU::OperandSemantics Sema, in decodeSrcOp()
207 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm | AMDGPU::EncValues::IS_VGPR, in decodeAV10()
208 false, 0, AMDGPU::OperandSemantics::INT, Decoder); in decodeAV10()
217 AMDGPU::OperandSemantics::INT, Decoder); in decodeSrcReg9()
227 AMDGPU::OperandSemantics::INT, Decoder); in decodeSrcA9()
237 AMDGPU::OperandSemantics::INT, Decoder); in decodeSrcAV10()
251 (AMDGPU::OperandSemantics)OperandSemantics, Decoder); in decodeSrcRegOrImm9()
262 (AMDGPU::OperandSemantics)OperandSemantics, Decoder); in decodeSrcRegOrImmA9()
271 (AMDGPU::OperandSemantics)OperandSemantics, Decoder); in decodeSrcRegOrImmDeferred9()
385 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); in IsAGPROperand()
387 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; in IsAGPROperand()
404 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 in decodeAVLdSt()
405 : AMDGPU::OpName::vdata; in decodeAVLdSt()
407 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); in decodeAVLdSt()
409 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); in decodeAVLdSt()
415 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); in decodeAVLdSt()
438 AMDGPU::OperandSemantics::FP64)); in decodeOperand_VSrc_f64()
521 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding) && in getInstruction()
525 if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem) && in getInstruction()
532 if (STI.hasFeature(AMDGPU::FeatureFmaMixInsts) && in getInstruction()
536 if (STI.hasFeature(AMDGPU::FeatureGFX940Insts) && in getInstruction()
540 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts) && in getInstruction()
590 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts) && in getInstruction()
594 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding) && in getInstruction()
622 AMDGPU::isVOPC64DPP(MI.getOpcode())) in getInstruction()
624 else if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) != in getInstruction()
631 if (AMDGPU::isMAC(MI.getOpcode())) { in getInstruction()
634 AMDGPU::OpName::src2_modifiers); in getInstruction()
637 if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp || in getInstruction()
638 MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp) { in getInstruction()
641 AMDGPU::OpName::src2_modifiers); in getInstruction()
645 !AMDGPU::hasGDS(STI)) { in getInstruction()
646 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::gds); in getInstruction()
651 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), in getInstruction()
652 AMDGPU::OpName::cpol); in getInstruction()
656 AMDGPU::CPol::GLC : 0; in getInstruction()
659 AMDGPU::OpName::cpol); in getInstruction()
668 (STI.hasFeature(AMDGPU::FeatureGFX90AInsts))) { in getInstruction()
671 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); in getInstruction()
682 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); in getInstruction()
692 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); in getInstruction()
694 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); in getInstruction()
725 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), in getInstruction()
726 AMDGPU::OpName::vdst_in); in getInstruction()
737 AMDGPU::OpName::vdst_in); in getInstruction()
742 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); in getInstruction()
752 if (STI.hasFeature(AMDGPU::FeatureGFX11Insts)) { in convertEXPInst()
755 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); in convertEXPInst()
756 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); in convertEXPInst()
761 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || in convertVINTERPInst()
762 MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx12 || in convertVINTERPInst()
763 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || in convertVINTERPInst()
764 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx12 || in convertVINTERPInst()
765 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || in convertVINTERPInst()
766 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx12 || in convertVINTERPInst()
767 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11 || in convertVINTERPInst()
768 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx12) { in convertVINTERPInst()
771 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); in convertVINTERPInst()
776 if (STI.hasFeature(AMDGPU::FeatureGFX9) || in convertSDWAInst()
777 STI.hasFeature(AMDGPU::FeatureGFX10)) { in convertSDWAInst()
778 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst)) in convertSDWAInst()
780 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); in convertSDWAInst()
781 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { in convertSDWAInst()
782 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); in convertSDWAInst()
785 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), in convertSDWAInst()
786 AMDGPU::OpName::sdst); in convertSDWAInst()
789 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); in convertSDWAInst()
808 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, in collectVOPModifiers()
809 AMDGPU::OpName::src1_modifiers, in collectVOPModifiers()
810 AMDGPU::OpName::src2_modifiers}; in collectVOPModifiers()
812 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); in collectVOPModifiers()
836 MRI.getRegClass(AMDGPU::VGPR_16RegClassID); in convertTrue16OpSel()
838 {{AMDGPU::OpName::src0, AMDGPU::OpName::src0_modifiers, in convertTrue16OpSel()
840 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_modifiers, in convertTrue16OpSel()
842 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_modifiers, in convertTrue16OpSel()
844 {AMDGPU::OpName::vdst, AMDGPU::OpName::src0_modifiers, in convertTrue16OpSel()
847 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, OpName); in convertTrue16OpSel()
848 int OpModsIdx = AMDGPU::getNamedOperandIdx(Opc, OpModsName); in convertTrue16OpSel()
860 unsigned RegIdx = OpEnc & AMDGPU::HWEncoding::REG_IDX_MASK; in convertTrue16OpSel()
872 auto OldIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::old); in isMacDPP()
876 assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2)); in isMacDPP()
878 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2), in isMacDPP()
890 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); in convertMacDPPInst()
892 AMDGPU::OpName::src2_modifiers); in convertMacDPPInst()
899 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in); in convertDPP8Inst()
901 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in); in convertDPP8Inst()
905 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { in convertDPP8Inst()
909 AMDGPU::OpName::op_sel); in convertDPP8Inst()
913 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) in convertDPP8Inst()
915 AMDGPU::OpName::src0_modifiers); in convertDPP8Inst()
918 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) in convertDPP8Inst()
920 AMDGPU::OpName::src1_modifiers); in convertDPP8Inst()
928 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in); in convertVOP3DPPInst()
930 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in); in convertVOP3DPPInst()
935 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { in convertVOP3DPPInst()
938 AMDGPU::OpName::op_sel); in convertVOP3DPPInst()
948 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), in convertMIMGInst()
949 AMDGPU::OpName::vdst); in convertMIMGInst()
951 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), in convertMIMGInst()
952 AMDGPU::OpName::vdata); in convertMIMGInst()
954 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); in convertMIMGInst()
955 int RsrcOpName = (TSFlags & SIInstrFlags::MIMG) ? AMDGPU::OpName::srsrc in convertMIMGInst()
956 : AMDGPU::OpName::rsrc; in convertMIMGInst()
957 int RsrcIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), RsrcOpName); in convertMIMGInst()
958 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), in convertMIMGInst()
959 AMDGPU::OpName::dmask); in convertMIMGInst()
961 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), in convertMIMGInst()
962 AMDGPU::OpName::tfe); in convertMIMGInst()
963 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), in convertMIMGInst()
964 AMDGPU::OpName::d16); in convertMIMGInst()
966 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); in convertMIMGInst()
967 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in convertMIMGInst()
968 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); in convertMIMGInst()
986 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); in convertMIMGInst()
988 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); in convertMIMGInst()
989 const AMDGPU::MIMGDimInfo *Dim = in convertMIMGInst()
990 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); in convertMIMGInst()
994 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); in convertMIMGInst()
998 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || in convertMIMGInst()
999 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA || in convertMIMGInst()
1000 Info->MIMGEncoding == AMDGPU::MIMGEncGfx12; in convertMIMGInst()
1006 if (!STI.hasFeature(AMDGPU::FeaturePartialNSAEncoding)) { in convertMIMGInst()
1020 if (D16 && AMDGPU::hasPackedD16(STI)) { in convertMIMGInst()
1031 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); in convertMIMGInst()
1036 unsigned NewVdata = AMDGPU::NoRegister; in convertMIMGInst()
1042 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); in convertMIMGInst()
1045 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, in convertMIMGInst()
1047 if (NewVdata == AMDGPU::NoRegister) { in convertMIMGInst()
1057 unsigned NewVAddrSA = AMDGPU::NoRegister; in convertMIMGInst()
1058 if (STI.hasFeature(AMDGPU::FeatureNSAEncoding) && (!IsNSA || IsPartialNSA) && in convertMIMGInst()
1061 unsigned VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0); in convertMIMGInst()
1065 NewVAddrSA = MRI.getMatchingSuperReg(VAddrSA, AMDGPU::sub0, in convertMIMGInst()
1073 if (NewVdata != AMDGPU::NoRegister) { in convertMIMGInst()
1100 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) in convertVOP3PDPPInst()
1101 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); in convertVOP3PDPPInst()
1104 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) in convertVOP3PDPPInst()
1106 AMDGPU::OpName::op_sel); in convertVOP3PDPPInst()
1108 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi)) in convertVOP3PDPPInst()
1110 AMDGPU::OpName::op_sel_hi); in convertVOP3PDPPInst()
1112 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo)) in convertVOP3PDPPInst()
1114 AMDGPU::OpName::neg_lo); in convertVOP3PDPPInst()
1116 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi)) in convertVOP3PDPPInst()
1118 AMDGPU::OpName::neg_hi); in convertVOP3PDPPInst()
1127 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old)) in convertVOPCDPPInst()
1128 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); in convertVOPCDPPInst()
1131 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) in convertVOPCDPPInst()
1133 AMDGPU::OpName::src0_modifiers); in convertVOPCDPPInst()
1136 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) in convertVOPCDPPInst()
1138 AMDGPU::OpName::src1_modifiers); in convertVOPCDPPInst()
1146 AMDGPU::OpName::immDeferred); in convertFMAanyK()
1151 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || in convertFMAanyK()
1152 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); in convertFMAanyK()
1153 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && in convertFMAanyK()
1176 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); in createRegOperand()
1196 case AMDGPU::SGPR_32RegClassID: in createSRegOperand()
1197 case AMDGPU::TTMP_32RegClassID: in createSRegOperand()
1199 case AMDGPU::SGPR_64RegClassID: in createSRegOperand()
1200 case AMDGPU::TTMP_64RegClassID: in createSRegOperand()
1203 case AMDGPU::SGPR_96RegClassID: in createSRegOperand()
1204 case AMDGPU::TTMP_96RegClassID: in createSRegOperand()
1205 case AMDGPU::SGPR_128RegClassID: in createSRegOperand()
1206 case AMDGPU::TTMP_128RegClassID: in createSRegOperand()
1209 case AMDGPU::SGPR_256RegClassID: in createSRegOperand()
1210 case AMDGPU::TTMP_256RegClassID: in createSRegOperand()
1213 case AMDGPU::SGPR_288RegClassID: in createSRegOperand()
1214 case AMDGPU::TTMP_288RegClassID: in createSRegOperand()
1215 case AMDGPU::SGPR_320RegClassID: in createSRegOperand()
1216 case AMDGPU::TTMP_320RegClassID: in createSRegOperand()
1217 case AMDGPU::SGPR_352RegClassID: in createSRegOperand()
1218 case AMDGPU::TTMP_352RegClassID: in createSRegOperand()
1219 case AMDGPU::SGPR_384RegClassID: in createSRegOperand()
1220 case AMDGPU::TTMP_384RegClassID: in createSRegOperand()
1221 case AMDGPU::SGPR_512RegClassID: in createSRegOperand()
1222 case AMDGPU::TTMP_512RegClassID: in createSRegOperand()
1242 return createRegOperand(AMDGPU::VGPR_16RegClassID, RegIdxInVGPR16); in createVGPR16Operand()
1250 AMDGPU::hasVOPD(STI) && in decodeMandatoryLiteralConstant()
1278 using namespace AMDGPU::EncValues; in decodeIntImmed()
1387 static int64_t getInlineImmVal16(unsigned Imm, AMDGPU::OperandSemantics Sema) { in getInlineImmVal16()
1388 return (Sema == AMDGPU::OperandSemantics::BF16) ? getInlineImmValBF16(Imm) in getInlineImmVal16()
1393 AMDGPU::OperandSemantics Sema) { in decodeFPImmed()
1394 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN && in decodeFPImmed()
1395 Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); in decodeFPImmed()
1415 using namespace AMDGPU; in getVgprClassId()
1440 using namespace AMDGPU; in getAgprClassId()
1466 using namespace AMDGPU; in getSgprClassId()
1490 using namespace AMDGPU; in getTtmpClassId()
1512 using namespace AMDGPU::EncValues; in getTTmpIdx()
1523 AMDGPU::OperandSemantics Sema) const { in decodeSrcOp()
1524 using namespace AMDGPU::EncValues; in decodeSrcOp()
1542 AMDGPU::OperandSemantics Sema) const { in decodeNonVGPRSrcOp()
1546 using namespace AMDGPU::EncValues; in decodeNonVGPRSrcOp()
1569 return decodeLiteralConstant(Sema == AMDGPU::OperandSemantics::FP64); in decodeNonVGPRSrcOp()
1590 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); in decodeVOPDDstYOp()
1600 using namespace AMDGPU; in decodeSpecialReg32()
1636 using namespace AMDGPU; in decodeSpecialReg64()
1669 AMDGPU::OperandSemantics Sema) const { in decodeSDWASrc()
1670 using namespace AMDGPU::SDWA; in decodeSDWASrc()
1671 using namespace AMDGPU::EncValues; in decodeSDWASrc()
1673 if (STI.hasFeature(AMDGPU::FeatureGFX9) || in decodeSDWASrc()
1674 STI.hasFeature(AMDGPU::FeatureGFX10)) { in decodeSDWASrc()
1704 if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) in decodeSDWASrc()
1710 return decodeSDWASrc(OPW16, Val, 16, AMDGPU::OperandSemantics::FP16); in decodeSDWASrc16()
1714 return decodeSDWASrc(OPW32, Val, 32, AMDGPU::OperandSemantics::FP32); in decodeSDWASrc32()
1718 using namespace AMDGPU::SDWA; in decodeSDWAVopcDst()
1720 assert((STI.hasFeature(AMDGPU::FeatureGFX9) || in decodeSDWAVopcDst()
1721 STI.hasFeature(AMDGPU::FeatureGFX10)) && in decodeSDWAVopcDst()
1724 bool IsWave64 = STI.hasFeature(AMDGPU::FeatureWavefrontSize64); in decodeSDWAVopcDst()
1739 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); in decodeSDWAVopcDst()
1743 return STI.hasFeature(AMDGPU::FeatureWavefrontSize64) in decodeBoolReg()
1753 if (Val != AMDGPU::DPP::DPP8_FI_0 && Val != AMDGPU::DPP::DPP8_FI_1) in decodeDpp8FI()
1759 using VersionField = AMDGPU::EncodingField<7, 0>; in decodeVersionImm()
1760 using W64Bit = AMDGPU::EncodingBit<13>; in decodeVersionImm()
1761 using W32Bit = AMDGPU::EncodingBit<14>; in decodeVersionImm()
1762 using MDPBit = AMDGPU::EncodingBit<15>; in decodeVersionImm()
1763 using Encoding = AMDGPU::EncodingFields<VersionField, W64Bit, W32Bit, MDPBit>; in decodeVersionImm()
1771 const auto &Versions = AMDGPU::UCVersion::getGFXVersions(); in decodeVersionImm()
1773 [Version = Version](const AMDGPU::UCVersion::GFXVersion &V) { in decodeVersionImm()
1794 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands); in isVI()
1797 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } in isGFX9()
1800 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts); in isGFX90A()
1803 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } in isGFX9Plus()
1805 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } in isGFX10()
1808 return AMDGPU::isGFX10Plus(STI); in isGFX10Plus()
1812 return STI.hasFeature(AMDGPU::FeatureGFX11); in isGFX11()
1816 return AMDGPU::isGFX11Plus(STI); in isGFX11Plus()
1820 return STI.hasFeature(AMDGPU::FeatureGFX12); in isGFX12()
1824 return AMDGPU::isGFX12Plus(STI); in isGFX12Plus()
1828 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch); in hasArchitectedFlatScratch()
1832 return AMDGPU::hasKernargPreload(STI); in hasKernargPreload()
1906 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI, EnableWavefrontSize32); in decodeCOMPUTE_PGM_RSRC1()
1937 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); in decodeCOMPUTE_PGM_RSRC1()
2271 if (CodeObjectVersion >= AMDGPU::AMDHSA_COV5) in decodeKernelDescriptorDirective()