Lines Matching +full:0 +full:xc400
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
76 UCVersionW64Expr = createConstantSymbolExpr("UC_VERSION_W64_BIT", 0x2000); in AMDGPUDisassembler()
77 UCVersionW32Expr = createConstantSymbolExpr("UC_VERSION_W32_BIT", 0x4000); in AMDGPUDisassembler()
78 UCVersionMDPExpr = createConstantSymbolExpr("UC_VERSION_MDP_BIT", 0x8000); in AMDGPUDisassembler()
114 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) in decodeSOPPBrTarget()
126 Offset = Imm & 0xFFFFF; in decodeSMEMOffset()
198 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)
200 // Decoder for registers. Imm(10-bit): Imm{7-0} is number of register,
201 // Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC).
208 false, 0, AMDGPU::OperandSemantics::INT, Decoder); in decodeAV10()
216 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, 0, in decodeSrcReg9()
226 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, 0, in decodeSrcA9()
230 // Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding
236 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm, false, 0, in decodeSrcAV10()
312 assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used"); in DECODE_OPERAND_REG_8()
315 unsigned RegIdx = Imm & 0xff; in DECODE_OPERAND_REG_8()
326 unsigned RegIdx = Imm & 0x7f; in DecodeVGPR_16_Lo128RegisterClass()
340 unsigned RegIdx = Imm & 0x7f; in decodeOperand_VSrcT16_Lo128()
344 Imm & 0xFF, false, 16)); in decodeOperand_VSrcT16_Lo128()
356 unsigned RegIdx = Imm & 0xff; in decodeOperand_VSrcT16()
360 Imm & 0xFF, false, 16)); in decodeOperand_VSrcT16()
378 if (OpIdx < 0) in IsAGPROperand()
485 Bytes = Bytes_.slice(0, MaxInstBytesNum); in getInstruction()
515 Bytes = Bytes_.slice(0, MaxInstBytesNum); in getInstruction()
573 Bytes = Bytes_.slice(0, MaxInstBytesNum); in getInstruction()
633 insertNamedMCOperand(MI, MCOperand::createImm(0), in getInstruction()
640 insertNamedMCOperand(MI, MCOperand::createImm(0), in getInstruction()
646 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::gds); in getInstruction()
656 AMDGPU::CPol::GLC : 0; in getInstruction()
675 MI.insert(TFEIter, MCOperand::createImm(0)); in getInstruction()
686 MI.insert(SWZIter, MCOperand::createImm(0)); in getInstruction()
696 if (VAddr0Idx >= 0 && NSAArgs > 0) { in getInstruction()
700 for (unsigned i = 0; i < NSAArgs; ++i) { in getInstruction()
755 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); in convertEXPInst()
756 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); in convertEXPInst()
771 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); in convertVINTERPInst()
780 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); in convertSDWAInst()
789 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); in convertSDWAInst()
795 unsigned OpSel = 0;
796 unsigned OpSelHi = 0;
797 unsigned NegLo = 0;
798 unsigned NegHi = 0;
811 for (int J = 0; J < 3; ++J) { in collectVOPModifiers()
823 } else if (J == 0) { in collectVOPModifiers()
869 constexpr int DST_IDX = 0; in isMacDPP()
890 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); in convertMacDPPInst()
891 insertNamedMCOperand(MI, MCOperand::createImm(0), in convertMacDPPInst()
901 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in); in convertDPP8Inst()
914 insertNamedMCOperand(MI, MCOperand::createImm(0), in convertDPP8Inst()
919 insertNamedMCOperand(MI, MCOperand::createImm(0), in convertDPP8Inst()
930 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in); in convertVOP3DPPInst()
1016 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; in convertMIMGInst()
1019 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); in convertMIMGInst()
1043 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; in convertMIMGInst()
1101 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); in convertVOP3PDPPInst()
1128 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); in convertVOPCDPPInst()
1132 insertNamedMCOperand(MI, MCOperand::createImm(0), in convertVOPCDPPInst()
1137 insertNamedMCOperand(MI, MCOperand::createImm(0), in convertVOPCDPPInst()
1148 for (unsigned I = 0; I < DescNumOps; ++I) { in convertFMAanyK()
1194 int shift = 0; in createSRegOperand()
1241 unsigned RegIdxInVGPR16 = RegIdx * 2 + (IsHi ? 1 : 0); in createVGPR16Operand()
1266 return errOperand(0, "cannot read literal, inst bytes left " + in decodeLiteralConstant()
1306 return 0x3e22f983; in getInlineImmVal32()
1331 return 0x3fc45f306dc9c882; in getInlineImmVal64()
1340 return 0x3800; in getInlineImmValF16()
1342 return 0xB800; in getInlineImmValF16()
1344 return 0x3C00; in getInlineImmValF16()
1346 return 0xBC00; in getInlineImmValF16()
1348 return 0x4000; in getInlineImmValF16()
1350 return 0xC000; in getInlineImmValF16()
1352 return 0x4400; in getInlineImmValF16()
1354 return 0xC400; in getInlineImmValF16()
1356 return 0x3118; in getInlineImmValF16()
1365 return 0x3F00; in getInlineImmValBF16()
1367 return 0xBF00; in getInlineImmValBF16()
1369 return 0x3F80; in getInlineImmValBF16()
1371 return 0xBF80; in getInlineImmValBF16()
1373 return 0x4000; in getInlineImmValBF16()
1375 return 0xC000; in getInlineImmValBF16()
1377 return 0x4080; in getInlineImmValBF16()
1379 return 0xC080; in getInlineImmValBF16()
1381 return 0x3E22; in getInlineImmValBF16()
1398 // ImmWidth 0 is a default case where operand should not allow immediates. in decodeFPImmed()
1402 case 0: in decodeFPImmed()
1535 return decodeNonVGPRSrcOp(Width, Val & 0xFF, MandatoryLiteral, ImmWidth, in decodeSrcOp()
1545 assert(Val < (1 << 8) && "9-bit Src encoding when Val{8} is 0"); in decodeNonVGPRSrcOp()
1550 static_assert(SGPR_MIN == 0); in decodeNonVGPRSrcOp()
1555 if (TTmpIdx >= 0) { in decodeNonVGPRSrcOp()
1585 // Bit 0 of DstY isn't stored in the instruction, because it's always the
1586 // opposite of bit 0 of DstX.
1730 if (TTmpIdx >= 0) { in decodeSDWAVopcDst()
1759 using VersionField = AMDGPU::EncodingField<7, 0>; in decodeVersionImm()
1865 } while (0)
1870 } while (0)
1878 getBitRangeFromMask((MASK), 0).c_str()); \
1880 } while (0)
1922 // are set to 0. So while disassembling we consider that: in decodeCOMPUTE_PGM_RSRC1()
1925 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) in decodeCOMPUTE_PGM_RSRC1()
1939 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; in decodeCOMPUTE_PGM_RSRC1()
1941 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; in decodeCOMPUTE_PGM_RSRC1()
1942 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; in decodeCOMPUTE_PGM_RSRC1()
2063 // Bits [0-3]. in decodeCOMPUTE_PGM_RSRC3()
2167 } while (0) in decodeKernelDescriptorDirective()
2169 uint16_t TwoByteBuffer = 0; in decodeKernelDescriptorDirective()
2170 uint32_t FourByteBuffer = 0; in decodeKernelDescriptorDirective()
2198 // 4 reserved bytes, must be 0. in decodeKernelDescriptorDirective()
2200 for (int I = 0; I < 4; ++I) { in decodeKernelDescriptorDirective()
2201 if (ReservedBytes[I] != 0) in decodeKernelDescriptorDirective()
2214 // 20 reserved bytes, must be 0. in decodeKernelDescriptorDirective()
2216 for (int I = 0; I < 20; ++I) { in decodeKernelDescriptorDirective()
2217 if (ReservedBytes[I] != 0) in decodeKernelDescriptorDirective()
2297 // 4 bytes from here are reserved, must be 0. in decodeKernelDescriptorDirective()
2299 for (int I = 0; I < 4; ++I) { in decodeKernelDescriptorDirective()
2300 if (ReservedBytes[I] != 0) in decodeKernelDescriptorDirective()
2316 if (Bytes.size() != 64 || KdAddress % 64 != 0) in decodeKernelDescriptor()
2338 DataExtractor::Cursor C(0); in decodeKernelDescriptor()