5341     return TokError("directive only supported for amdgcn architecture");  in ParseDirectiveAMDGCNTarget()
5428     return TokError("directive only supported for amdgcn architecture");  in ParseDirectiveAMDHSAKernel()
5431     return TokError("directive only supported for amdhsa OS");  in ParseDirectiveAMDHSAKernel()
5479       return TokError(".amdhsa_ directives cannot be repeated");  in ParseDirectiveAMDHSAKernel()
5799     return TokError(".amdhsa_next_free_vgpr directive is required");  in ParseDirectiveAMDHSAKernel()
5802     return TokError(".amdhsa_next_free_sgpr directive is required");  in ParseDirectiveAMDHSAKernel()
5837     return TokError("amdgpu_user_sgpr_count smaller than than implied by "  in ParseDirectiveAMDHSAKernel()
5844     return TokError("too many user SGPRs enabled");  in ParseDirectiveAMDHSAKernel()
5852     return TokError("Kernarg size should be resolvable");  in ParseDirectiveAMDHSAKernel()
5856     return TokError("Kernarg preload length + offset is larger than the "  in ParseDirectiveAMDHSAKernel()
5861       return TokError(".amdhsa_accum_offset directive is required");  in ParseDirectiveAMDHSAKernel()
5867       return TokError("accum_offset should be in range [4..256] in "  in ParseDirectiveAMDHSAKernel()
5875       return TokError("accum_offset exceeds total VGPR allocation");  in ParseDirectiveAMDHSAKernel()
5889       return TokError("shared_vgpr_count directive not valid on "  in ParseDirectiveAMDHSAKernel()
5896       return TokError("shared_vgpr_count*2 + "  in ParseDirectiveAMDHSAKernel()
5929     return TokError(Err.str());  in ParseAMDKernelCodeTValue()
5936         return TokError("enable_wavefront_size32=1 is only allowed on GFX10+");  in ParseAMDKernelCodeTValue()
5938         return TokError("enable_wavefront_size32=1 requires +WavefrontSize32");  in ParseAMDKernelCodeTValue()
5941         return TokError("enable_wavefront_size32=0 requires +WavefrontSize64");  in ParseAMDKernelCodeTValue()
5948         return TokError("wavefront_size=5 is only allowed on GFX10+");  in ParseAMDKernelCodeTValue()
5950         return TokError("wavefront_size=5 requires +WavefrontSize32");  in ParseAMDKernelCodeTValue()
5953         return TokError("wavefront_size=6 requires +WavefrontSize64");  in ParseAMDKernelCodeTValue()
6060     return TokError(Twine("expected directive ") +  in ParseToEndDirective()
6094       return TokError(Twine("invalid value in ") +  in ParseDirectivePALMetadata()
6098       return TokError(Twine("expected an even number of values in ") +  in ParseDirectivePALMetadata()
6102       return TokError(Twine("invalid value in ") +  in ParseDirectivePALMetadata()
6121     return TokError("expected identifier in directive");  in ParseDirectiveAMDGPULDS()