4061   const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);  in validateMovrels()  local
4062   assert(Src0Idx != -1);  in validateMovrels()
4065   const MCOperand &Src0 = Inst.getOperand(Src0Idx);  in validateMovrels()
4088   const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);  in validateMAIAccWrite()  local
4089   assert(Src0Idx != -1);  in validateMAIAccWrite()
4091   const MCOperand &Src0 = Inst.getOperand(Src0Idx);  in validateMAIAccWrite()
4495   const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);  in validateSOPLiteral()  local
4498   const int OpIndices[] = { Src0Idx, Src1Idx };  in validateSOPLiteral()
4841   int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sdst);  in validateWaitCnt()  local
4842   assert(Src0Idx >= 0 && Inst.getOperand(Src0Idx).isReg());  in validateWaitCnt()
4843   auto Reg = mc2PseudoReg(Inst.getOperand(Src0Idx).getReg());  in validateWaitCnt()