1586   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1734   bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);
1746   bool validateMIMGDataSize(const MCInst &Inst, const SMLoc &IDLoc);
1747   bool validateMIMGAddrSize(const MCInst &Inst, const SMLoc &IDLoc);
1766                              const SMLoc &IDLoc);
1782   bool checkUnsupportedInstruction(StringRef Name, const SMLoc &IDLoc);
3859                                            const SMLoc &IDLoc) {  in validateMIMGDataSize()  argument
3902   Error(IDLoc, Twine("image data size does not match ") + Modifiers);  in validateMIMGDataSize()
3907                                            const SMLoc &IDLoc) {  in validateMIMGAddrSize()  argument
3933     Error(IDLoc, "image address size does not match a16");  in validateMIMGAddrSize()
3971   Error(IDLoc, "image address size does not match dim and a16");  in validateMIMGAddrSize()
4905                                             const SMLoc &IDLoc) {  in validateCoherencyBits()  argument
4924       Error(IDLoc, "invalid cache policy for SMEM instruction");  in validateCoherencyBits()
4948       Error(IDLoc, isGFX940() ? "instruction must use sc0"  in validateCoherencyBits()
5053                                           const SMLoc &IDLoc,  in validateInstruction()  argument
5107   if (!validateMIMGDataSize(Inst, IDLoc)) {  in validateInstruction()
5110   if (!validateMIMGAddrSize(Inst, IDLoc))  in validateInstruction()
5137   if (!validateCoherencyBits(Inst, Operands, IDLoc)) {  in validateInstruction()
5142     Error(IDLoc, getFeatureBits()[AMDGPU::FeatureGFX90AInsts]  in validateInstruction()
5149     Error(IDLoc,  in validateInstruction()
5162     Error(IDLoc, "ABS not allowed in VOP3B instructions");  in validateInstruction()
5203                                                   const SMLoc &IDLoc) {  in checkUnsupportedInstruction()  argument
5218     return Error(IDLoc,  in checkUnsupportedInstruction()
5234       return Error(IDLoc, "instruction requires wavesize=32");  in checkUnsupportedInstruction()
5239     return Error(IDLoc, "instruction not supported on this GPU");  in checkUnsupportedInstruction()
5244   return Error(IDLoc, "invalid instruction" + Suggestion);  in checkUnsupportedInstruction()
5258 bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,  in MatchAndEmitInstruction()  argument
5284     if (!validateInstruction(Inst, IDLoc, Operands)) {  in MatchAndEmitInstruction()
5287     Inst.setLoc(IDLoc);  in MatchAndEmitInstruction()
5293   if (checkUnsupportedInstruction(Mnemo, IDLoc)) {  in MatchAndEmitInstruction()
5303     return Error(IDLoc, "operands are not valid for this GPU or mode");  in MatchAndEmitInstruction()
5306     SMLoc ErrorLoc = IDLoc;  in MatchAndEmitInstruction()
5309         return Error(IDLoc, "too few operands for instruction");  in MatchAndEmitInstruction()
5313         ErrorLoc = IDLoc;  in MatchAndEmitInstruction()