Lines Matching refs:ExprVal
5482 const MCExpr *ExprVal; in ParseDirectiveAMDHSAKernel() local
5483 if (getParser().parseExpression(ExprVal)) in ParseDirectiveAMDHSAKernel()
5491 if ((EvaluatableExpr = ExprVal->evaluateAsAbsolute(IVal))) { in ParseDirectiveAMDHSAKernel()
5514 KD.group_segment_fixed_size = ExprVal; in ParseDirectiveAMDHSAKernel()
5519 KD.private_segment_fixed_size = ExprVal; in ParseDirectiveAMDHSAKernel()
5523 KD.kernarg_size = ExprVal; in ParseDirectiveAMDHSAKernel()
5535 ExprVal, ValRange); in ParseDirectiveAMDHSAKernel()
5545 PARSE_BITS_ENTRY(KD.kernarg_preload, KERNARG_PRELOAD_SPEC_LENGTH, ExprVal, in ParseDirectiveAMDHSAKernel()
5558 PARSE_BITS_ENTRY(KD.kernarg_preload, KERNARG_PRELOAD_SPEC_OFFSET, ExprVal, in ParseDirectiveAMDHSAKernel()
5565 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR, ExprVal, in ParseDirectiveAMDHSAKernel()
5572 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR, ExprVal, in ParseDirectiveAMDHSAKernel()
5580 ExprVal, ValRange); in ParseDirectiveAMDHSAKernel()
5586 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID, ExprVal, in ParseDirectiveAMDHSAKernel()
5598 ExprVal, ValRange); in ParseDirectiveAMDHSAKernel()
5605 ExprVal, ValRange); in ParseDirectiveAMDHSAKernel()
5614 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32, ExprVal, in ParseDirectiveAMDHSAKernel()
5618 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK, ExprVal, in ParseDirectiveAMDHSAKernel()
5626 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT, ExprVal, in ParseDirectiveAMDHSAKernel()
5635 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT, ExprVal, in ParseDirectiveAMDHSAKernel()
5639 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, ExprVal, in ParseDirectiveAMDHSAKernel()
5643 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y, ExprVal, in ParseDirectiveAMDHSAKernel()
5647 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z, ExprVal, in ParseDirectiveAMDHSAKernel()
5651 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO, ExprVal, in ParseDirectiveAMDHSAKernel()
5655 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID, ExprVal, in ParseDirectiveAMDHSAKernel()
5659 NextFreeVGPR = ExprVal; in ParseDirectiveAMDHSAKernel()
5662 NextFreeSGPR = ExprVal; in ParseDirectiveAMDHSAKernel()
5666 AccumOffset = ExprVal; in ParseDirectiveAMDHSAKernel()
5670 ReserveVCC = ExprVal; in ParseDirectiveAMDHSAKernel()
5680 ReserveFlatScr = ExprVal; in ParseDirectiveAMDHSAKernel()
5691 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32, ExprVal, in ParseDirectiveAMDHSAKernel()
5695 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64, ExprVal, in ParseDirectiveAMDHSAKernel()
5699 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32, ExprVal, in ParseDirectiveAMDHSAKernel()
5703 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64, ExprVal, in ParseDirectiveAMDHSAKernel()
5709 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP, ExprVal, in ParseDirectiveAMDHSAKernel()
5715 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE, ExprVal, in ParseDirectiveAMDHSAKernel()
5721 COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL, ExprVal, in ParseDirectiveAMDHSAKernel()
5727 ExprVal, ValRange); in ParseDirectiveAMDHSAKernel()
5732 COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE, ExprVal, in ParseDirectiveAMDHSAKernel()
5738 COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED, ExprVal, in ParseDirectiveAMDHSAKernel()
5744 COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS, ExprVal, in ParseDirectiveAMDHSAKernel()
5753 COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT, ExprVal, in ParseDirectiveAMDHSAKernel()
5759 ExprVal, ValRange); in ParseDirectiveAMDHSAKernel()
5763 ExprVal, ValRange); in ParseDirectiveAMDHSAKernel()
5768 ExprVal, ValRange); in ParseDirectiveAMDHSAKernel()
5772 ExprVal, ValRange); in ParseDirectiveAMDHSAKernel()
5776 ExprVal, ValRange); in ParseDirectiveAMDHSAKernel()
5780 ExprVal, ValRange); in ParseDirectiveAMDHSAKernel()
5784 ExprVal, ValRange); in ParseDirectiveAMDHSAKernel()
5789 COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN, ExprVal, in ParseDirectiveAMDHSAKernel()
7292 int64_t ExprVal; in parseDepCtr() local
7293 if (!parseExpr(ExprVal)) in parseDepCtr()
7297 int CntVal = encodeDepCtr(DepCtrName, ExprVal, UsedOprMask, getSTI()); in parseDepCtr()