Lines Matching refs:getOptLevel

907   return getStandardCSEConfigForOpt(TM->getOptLevel());  in getCSEConfig()
989   if (getOptLevel() == CodeGenOptLevel::Aggressive)  in addEarlyCSEOrGVNPass()
1051   if (TM.getOptLevel() > CodeGenOptLevel::None)  in addIRPasses()
1056       (TM.getOptLevel() >= CodeGenOptLevel::Less) &&  in addIRPasses()
1063   if (TM.getOptLevel() > CodeGenOptLevel::None) {  in addIRPasses()
1085     if (TM.getOptLevel() > CodeGenOptLevel::Less)  in addIRPasses()
1154   if (TM->getOptLevel() > CodeGenOptLevel::None)  in addPreISel()
1160   addPass(createAMDGPUISelDag(getAMDGPUTargetMachine(), getOptLevel()));  in addInstSelector()
1205   if (TM->getOptLevel() > CodeGenOptLevel::None)  in addPreISel()
1208   if (TM->getOptLevel() > CodeGenOptLevel::None)  in addPreISel()
1231   if (TM->getOptLevel() > CodeGenOptLevel::Less)  in addPreISel()
1277   addPass(new IRTranslator(getOptLevel()));  in addIRTranslator()
1282   bool IsOptNone = getOptLevel() == CodeGenOptLevel::None;  in addPreLegalizeMachineIR()
1293   bool IsOptNone = getOptLevel() == CodeGenOptLevel::None;  in addPreRegBankSelect()
1304   bool IsOptNone = getOptLevel() == CodeGenOptLevel::None;  in addPreGlobalInstructionSelect()
1309   addPass(new InstructionSelect(getOptLevel()));  in addGlobalInstructionSelect()
1349   if (TM->getOptLevel() > CodeGenOptLevel::Less)  in addOptimizedRegAlloc()
1461   if (getOptLevel() > CodeGenOptLevel::None)  in addPostRegAlloc()
1467   if (TM->getOptLevel() > CodeGenOptLevel::None)  in addPreSched2()
1480   if (getOptLevel() > CodeGenOptLevel::None)  in addPreEmitPass()
1486   if (getOptLevel() > CodeGenOptLevel::None)  in addPreEmitPass()