672         PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));  in registerPassBuilderCallbacks()
674           PM.addPass(HipStdParAcceleratorCodeSelectionPass());  in registerPassBuilderCallbacks()
679         PM.addPass(AMDGPUPrintfRuntimeBindingPass());  in registerPassBuilderCallbacks()
684         PM.addPass(AMDGPUUnifyMetadataPass());  in registerPassBuilderCallbacks()
687           PM.addPass(InternalizePass(mustPreserveGV));  in registerPassBuilderCallbacks()
688           PM.addPass(GlobalDCEPass());  in registerPassBuilderCallbacks()
692           PM.addPass(AMDGPUAlwaysInlinePass());  in registerPassBuilderCallbacks()
700         FPM.addPass(AMDGPUUseNativeCallsPass());  in registerPassBuilderCallbacks()
702           FPM.addPass(AMDGPUSimplifyLibCallsPass());  in registerPassBuilderCallbacks()
717           FPM.addPass(AMDGPUPromoteKernelArgumentsPass());  in registerPassBuilderCallbacks()
721         FPM.addPass(InferAddressSpacesPass());  in registerPassBuilderCallbacks()
725         FPM.addPass(AMDGPULowerKernelAttributesPass());  in registerPassBuilderCallbacks()
731           FPM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));  in registerPassBuilderCallbacks()
734         PM.addPass(createCGSCCToFunctionPassAdaptor(std::move(FPM)));  in registerPassBuilderCallbacks()
741           MPM.addPass(AMDGPUAttributorPass(*this));  in registerPassBuilderCallbacks()
751           PM.addPass(AMDGPULowerModuleLDSPass(*this));  in registerPassBuilderCallbacks()
858   MPM.addPass(AMDGPUSplitModulePass(NumParts, ModuleCallback));  in splitModule()
990     addPass(createGVNPass());  in addEarlyCSEOrGVNPass()
992     addPass(createEarlyCSEPass());  in addEarlyCSEOrGVNPass()
997     addPass(createLoopDataPrefetchPass());  in addStraightLineScalarOptimizationPasses()
998   addPass(createSeparateConstOffsetFromGEPPass());  in addStraightLineScalarOptimizationPasses()
1001   addPass(createStraightLineStrengthReducePass());  in addStraightLineScalarOptimizationPasses()
1006   addPass(createNaryReassociatePass());  in addStraightLineScalarOptimizationPasses()
1009   addPass(createEarlyCSEPass());  in addStraightLineScalarOptimizationPasses()
1017     addPass(createAMDGPURemoveIncompatibleFunctionsPass(&TM));  in addIRPasses()
1024   addPass(createAMDGPUPrintfRuntimeBinding());  in addIRPasses()
1026     addPass(createAMDGPUCtorDtorLoweringLegacyPass());  in addIRPasses()
1029     addPass(createAMDGPUImageIntrinsicOptimizerPass(&TM));  in addIRPasses()
1033   addPass(createExpandVariadicsPass(ExpandVariadicsMode::Lowering));  in addIRPasses()
1036   addPass(createAMDGPUAlwaysInlinePass());  in addIRPasses()
1037   addPass(createAlwaysInlinerLegacyPass());  in addIRPasses()
1041     addPass(createR600OpenCLImageTypeLoweringPass());  in addIRPasses()
1044   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());  in addIRPasses()
1048     addPass(createAMDGPULowerModuleLDSLegacyPass(&TM));  in addIRPasses()
1052     addPass(createInferAddressSpacesPass());  in addIRPasses()
1058     addPass(createAMDGPUAtomicOptimizerPass(AMDGPUAtomicOptimizerStrategy));  in addIRPasses()
1061   addPass(createAtomicExpandLegacyPass());  in addIRPasses()
1064     addPass(createAMDGPUPromoteAlloca());  in addIRPasses()
1070       addPass(createAMDGPUAAWrapperPass());  in addIRPasses()
1071       addPass(createExternalAAWrapperPass([](Pass &P, Function &,  in addIRPasses()
1080       addPass(createAMDGPUCodeGenPreparePass());  in addIRPasses()
1086       addPass(createLICMPass());  in addIRPasses()
1111     addPass(createAMDGPUAnnotateKernelFeaturesPass());  in addCodeGenPrepare()
1116     addPass(createAMDGPULowerKernelArgumentsPass());  in addCodeGenPrepare()
1135     addPass(createAMDGPULowerBufferFatPointersPass());  in addCodeGenPrepare()
1138     addPass(new DummyCGSCCPass());  in addCodeGenPrepare()
1144     addPass(createLoadStoreVectorizerPass());  in addCodeGenPrepare()
1150   addPass(createLowerSwitchPass());  in addCodeGenPrepare()
1155     addPass(createFlattenCFGPass());  in addPreISel()
1160   addPass(createAMDGPUISelDag(getAMDGPUTargetMachine(), getOptLevel()));  in addInstSelector()
1206     addPass(createSinkingPass());  in addPreISel()
1209     addPass(createAMDGPULateCodeGenPreparePass());  in addPreISel()
1213   addPass(&AMDGPUUnifyDivergentExitNodesID);  in addPreISel()
1216       addPass(createFixIrreduciblePass());  in addPreISel()
1217       addPass(createUnifyLoopExitsPass());  in addPreISel()
1219     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions  in addPreISel()
1221   addPass(createAMDGPUAnnotateUniformValues());  in addPreISel()
1223     addPass(createSIAnnotateControlFlowPass());  in addPreISel()
1227     addPass(createAMDGPURewriteUndefForPHILegacyPass());  in addPreISel()
1229   addPass(createLCSSAPass());  in addPreISel()
1232     addPass(&AMDGPUPerfHintAnalysisID);  in addPreISel()
1247   addPass(&SIFoldOperandsID);  in addMachineSSAOptimization()
1249     addPass(&GCNDPPCombineID);  in addMachineSSAOptimization()
1250   addPass(&SILoadStoreOptimizerID);  in addMachineSSAOptimization()
1252     addPass(&SIPeepholeSDWAID);  in addMachineSSAOptimization()
1253     addPass(&EarlyMachineLICMID);  in addMachineSSAOptimization()
1254     addPass(&MachineCSEID);  in addMachineSSAOptimization()
1255     addPass(&SIFoldOperandsID);  in addMachineSSAOptimization()
1257   addPass(&DeadMachineInstructionElimID);  in addMachineSSAOptimization()
1258   addPass(createSIShrinkInstructionsPass());  in addMachineSSAOptimization()
1263     addPass(&EarlyIfConverterID);  in addILPOpts()
1271   addPass(&SIFixSGPRCopiesID);  in addInstSelector()
1272   addPass(createSILowerI1CopiesPass());  in addInstSelector()
1277   addPass(new IRTranslator(getOptLevel()));  in addIRTranslator()
1283   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));  in addPreLegalizeMachineIR()
1284   addPass(new Localizer());  in addPreLegalizeMachineIR()
1288   addPass(new Legalizer());  in addLegalizeMachineIR()
1294   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));  in addPreRegBankSelect()
1295   addPass(createAMDGPUGlobalISelDivergenceLoweringPass());  in addPreRegBankSelect()
1299   addPass(new AMDGPURegBankSelect());  in addRegBankSelect()
1305   addPass(createAMDGPURegBankCombiner(IsOptNone));  in addPreGlobalInstructionSelect()
1309   addPass(new InstructionSelect(getOptLevel()));  in addGlobalInstructionSelect()
1315     addPass(createAMDGPUMachineCFGStructurizerPass());  in addPreRegAlloc()
1370   addPass(&SILowerWWMCopiesID);  in addPreRewrite()
1372     addPass(&GCNNSAReassignID);  in addPreRewrite()
1417   addPass(&GCNPreRALongBranchRegID);  in addRegAssignAndRewriteFast()
1419   addPass(createSGPRAllocPass(false));  in addRegAssignAndRewriteFast()
1422   addPass(&SILowerSGPRSpillsID);  in addRegAssignAndRewriteFast()
1423   addPass(&SIPreAllocateWWMRegsID);  in addRegAssignAndRewriteFast()
1425   addPass(createVGPRAllocPass(false));  in addRegAssignAndRewriteFast()
1427   addPass(&SILowerWWMCopiesID);  in addRegAssignAndRewriteFast()
1435   addPass(&GCNPreRALongBranchRegID);  in addRegAssignAndRewriteOptimized()
1437   addPass(createSGPRAllocPass(true));  in addRegAssignAndRewriteOptimized()
1443   addPass(createVirtRegRewriter(false));  in addRegAssignAndRewriteOptimized()
1446   addPass(&SILowerSGPRSpillsID);  in addRegAssignAndRewriteOptimized()
1447   addPass(&SIPreAllocateWWMRegsID);  in addRegAssignAndRewriteOptimized()
1449   addPass(createVGPRAllocPass(true));  in addRegAssignAndRewriteOptimized()
1452   addPass(&VirtRegRewriterID);  in addRegAssignAndRewriteOptimized()
1454   addPass(&AMDGPUMarkLastScratchLoadID);  in addRegAssignAndRewriteOptimized()
1460   addPass(&SIFixVGPRCopiesID);  in addPostRegAlloc()
1462     addPass(&SIOptimizeExecMaskingID);  in addPostRegAlloc()
1468     addPass(createSIShrinkInstructionsPass());  in addPreSched2()
1469   addPass(&SIPostRABundlerID);  in addPreSched2()
1474     addPass(&GCNCreateVOPDID);  in addPreEmitPass()
1475   addPass(createSIMemoryLegalizerPass());  in addPreEmitPass()
1476   addPass(createSIInsertWaitcntsPass());  in addPreEmitPass()
1478   addPass(createSIModeRegisterPass());  in addPreEmitPass()
1481     addPass(&SIInsertHardClausesID);  in addPreEmitPass()
1483   addPass(&SILateBranchLoweringPassID);  in addPreEmitPass()
1485     addPass(createAMDGPUSetWavePriorityPass());  in addPreEmitPass()
1487     addPass(&SIPreEmitPeepholeID);  in addPreEmitPass()
1496   addPass(&PostRAHazardRecognizerID);  in addPreEmitPass()
1499     addPass(&AMDGPUInsertSingleUseVDSTID);  in addPreEmitPass()
1502     addPass(&AMDGPUInsertDelayAluID);  in addPreEmitPass()
1504   addPass(&BranchRelaxationPassID);  in addPreEmitPass()