158       const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, *RBI.TRI);  in applyBank()  local
159       assert(DstBank != &AMDGPU::VCCRegBank);  in applyBank()
1064   const RegisterBank *DstBank =  in applyMappingLoad()  local
1066   if (DstBank == &AMDGPU::SGPRRegBank) {  in applyMappingLoad()
1091     ApplyRegBankMapping ApplyBank(B, *this, MRI, DstBank);  in applyMappingLoad()
1466   const RegisterBank *DstBank =  in applyMappingBFE()  local
1468   if (DstBank == &AMDGPU::VGPRRegBank) {  in applyMappingBFE()
1621   const RegisterBank &DstBank =  in applyMappingMAD_64_32()  local
1653     MRI.setRegBank(Src2Lo, DstBank);  in applyMappingMAD_64_32()
1654     MRI.setRegBank(Src2Hi, DstBank);  in applyMappingMAD_64_32()
1667     MRI.setRegBank(DstLo, DstBank);  in applyMappingMAD_64_32()
1672     MRI.setRegBank(DstHi, DstBank);  in applyMappingMAD_64_32()
1944   const RegisterBank &DstBank =  in foldExtractEltToCmpSelect()  local
1950     (DstBank == AMDGPU::SGPRRegBank &&  in foldExtractEltToCmpSelect()
1985         MRI.setRegBank(S->getOperand(N).getReg(), DstBank);  in foldExtractEltToCmpSelect()
1994     MRI.setRegBank(DstReg, DstBank);  in foldExtractEltToCmpSelect()
1997   MRI.setRegBank(MI.getOperand(0).getReg(), DstBank);  in foldExtractEltToCmpSelect()
2042   const RegisterBank &DstBank =  in foldInsertEltToCmpSelect()  local
2050     (DstBank == AMDGPU::SGPRRegBank &&  in foldInsertEltToCmpSelect()
2082       Register Op0 = constrainRegToBank(MRI, B, InsRegs[L], DstBank);  in foldInsertEltToCmpSelect()
2084       Op1 = constrainRegToBank(MRI, B, Op1, DstBank);  in foldInsertEltToCmpSelect()
2087       MRI.setRegBank(Select, DstBank);  in foldInsertEltToCmpSelect()
2098     MRI.setRegBank(Vec->getOperand(0).getReg(), DstBank);  in foldInsertEltToCmpSelect()
2102   MRI.setRegBank(MI.getOperand(0).getReg(), DstBank);  in foldInsertEltToCmpSelect()
2190     const RegisterBank *DstBank =  in applyMappingImpl()  local
2192     if (DstBank == &AMDGPU::VCCRegBank)  in applyMappingImpl()
2210     MRI.setRegBank(NewDstReg, *DstBank);  in applyMappingImpl()
2221     const RegisterBank *DstBank =  in applyMappingImpl()  local
2223     if (DstBank == &AMDGPU::VCCRegBank) {  in applyMappingImpl()
2251     ApplyRegBankMapping ApplyBank(B, *this, MRI, DstBank);  in applyMappingImpl()
2275     const RegisterBank *DstBank =  in applyMappingImpl()  local
2277     if (DstBank != &AMDGPU::SGPRRegBank)  in applyMappingImpl()
2390       const RegisterBank *DstBank =  in applyMappingImpl()  local
2392       if (DstBank == &AMDGPU::VCCRegBank)  in applyMappingImpl()
2396       ApplyRegBankMapping ApplyBank(B, *this, MRI, DstBank);  in applyMappingImpl()
2489     const RegisterBank *DstBank =  in applyMappingImpl()  local
2491     if (DstBank == &AMDGPU::VGPRRegBank)  in applyMappingImpl()
2562     const RegisterBank *DstBank =  in applyMappingImpl()  local
2567     if (DstBank == &AMDGPU::SGPRRegBank) {  in applyMappingImpl()
2648     const RegisterBank *DstBank =  in applyMappingImpl()  local
2650     if (DstBank == &AMDGPU::SGPRRegBank)  in applyMappingImpl()
2672     const RegisterBank *DstBank =  in applyMappingImpl()  local
2674     if (DstBank == &AMDGPU::SGPRRegBank)  in applyMappingImpl()
2757       const RegisterBank *DstBank = &AMDGPU::VGPRRegBank;  in applyMappingImpl()  local
2769       MRI.setRegBank(True.getReg(0), *DstBank);  in applyMappingImpl()
2770       MRI.setRegBank(False.getReg(0), *DstBank);  in applyMappingImpl()
2771       MRI.setRegBank(DstReg, *DstBank);  in applyMappingImpl()
2778         MRI.setRegBank(Sel.getReg(0), *DstBank);  in applyMappingImpl()
2807     const RegisterBank *DstBank = DstMapping.BreakDown[0].RegBank;  in applyMappingImpl()  local
2834     const bool NeedCopyToVGPR = DstBank == &AMDGPU::VGPRRegBank &&  in applyMappingImpl()
2881     MRI.setRegBank(DstReg, *DstBank);  in applyMappingImpl()
2994     const RegisterBank *DstBank =  in applyMappingImpl()  local
3003     MRI.setRegBank(InsLo.getReg(0), *DstBank);  in applyMappingImpl()
3004     MRI.setRegBank(InsHi.getReg(0), *DstBank);  in applyMappingImpl()
3740     const RegisterBank *DstBank = getRegBank(MI.getOperand(0).getReg(), MRI,  in getInstrMapping()  local
3745     if (!DstBank)  in getInstrMapping()
3746       DstBank = SrcBank;  in getInstrMapping()
3750         cannotCopy(*DstBank, *SrcBank, TypeSize::getFixed(Size)))  in getInstrMapping()
3753     const ValueMapping &ValMap = getValueMapping(0, Size, *DstBank);  in getInstrMapping()
3796     if (const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI))  in getInstrMapping()  local
3797       ResultBank = DstBank->getID();  in getInstrMapping()
3841       const RegisterBank *DstBank  in getInstrMapping()  local
3847       if (DstBank) {  in getInstrMapping()
3848         TargetBankID = DstBank->getID();  in getInstrMapping()
3849         if (DstBank == &AMDGPU::VCCRegBank) {  in getInstrMapping()
4190     unsigned DstBank;  in getInstrMapping()  local
4195       DstBank = AMDGPU::SGPRRegBankID;  in getInstrMapping()
4198       DstBank = AMDGPU::VGPRRegBankID;  in getInstrMapping()
4204     OpdsMapping[0] = AMDGPU::getValueMappingSGPR64Only(DstBank, DstSize);  in getInstrMapping()
4235     unsigned DstBank = getRegBankID(MI.getOperand(0).getReg(), MRI,  in getInstrMapping()  local
4253     bool CanUseSCC = DstBank == AMDGPU::SGPRRegBankID &&  in getInstrMapping()
4258     DstBank = CanUseSCC ? AMDGPU::SGPRRegBankID : AMDGPU::VCCRegBankID;  in getInstrMapping()
4265     OpdsMapping[0] = AMDGPU::getValueMapping(DstBank, ResultSize);  in getInstrMapping()