Lines Matching refs:addImm
156 .addImm(ConstVal->Value.getBoolValue() ? -1 : 0); in selectCOPY()
168 .addImm(NoMods) in selectCOPY()
169 .addImm(1) in selectCOPY()
170 .addImm(NoMods) in selectCOPY()
172 .addImm(NoMods); in selectCOPY()
174 .addImm(NoMods) in selectCOPY()
175 .addImm(0) in selectCOPY()
176 .addImm(NoMods) in selectCOPY()
178 .addImm(NoMods); in selectCOPY()
183 .addImm(1) in selectCOPY()
189 .addImm(0) in selectCOPY()
229 .addImm(0); in selectCOPY_SCC_VCC()
253 BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg).addImm(0); in selectCOPY_VCC_SCC()
269 .addImm(0); in selectCOPY_VCC_SCC()
451 .addImm(0); in selectG_ADD_SUB()
486 .addImm(0); in selectG_ADD_SUB()
492 .addImm(0); in selectG_ADD_SUB()
500 .addImm(AMDGPU::sub0) in selectG_ADD_SUB()
502 .addImm(AMDGPU::sub1); in selectG_ADD_SUB()
660 MIB.addImm(SubRegs[I]); in selectG_MERGE_VALUES()
769 BuildMI(*BB, &MI, DL, TII.get(AMDGPU::V_MOV_B32_e32), Dst).addImm(Imm); in selectG_BUILD_VECTOR()
775 BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_MOV_B32), Dst).addImm(Imm); in selectG_BUILD_VECTOR()
801 .addImm(0xFFFF) in selectG_BUILD_VECTOR()
808 .addImm(16) in selectG_BUILD_VECTOR()
853 .addImm(16) in selectG_BUILD_VECTOR()
937 .addImm(SubReg); in selectG_INSERT()
993 .addImm(2) in selectInterpP1F16()
994 .addImm(MI.getOperand(4).getImm()) // $attr in selectInterpP1F16()
995 .addImm(MI.getOperand(3).getImm()); // $attrchan in selectInterpP1F16()
998 .addImm(0) // $src0_modifiers in selectInterpP1F16()
1000 .addImm(MI.getOperand(4).getImm()) // $attr in selectInterpP1F16()
1001 .addImm(MI.getOperand(3).getImm()) // $attrchan in selectInterpP1F16()
1002 .addImm(0) // $src2_modifiers in selectInterpP1F16()
1004 .addImm(MI.getOperand(5).getImm()) // $high in selectInterpP1F16()
1005 .addImm(0) // $clamp in selectInterpP1F16()
1006 .addImm(0); // $omod in selectInterpP1F16()
1037 MIB.addImm(ConstSelect->Value.getSExtValue() & in selectWritelane()
1047 MIB.addImm(ConstVal->Value.getSExtValue()); in selectWritelane()
1097 .addImm(0) // $src0_modifiers in selectDivScale()
1099 .addImm(0) // $src1_modifiers in selectDivScale()
1101 .addImm(0) // $src2_modifiers in selectDivScale()
1103 .addImm(0) // $clamp in selectDivScale()
1104 .addImm(0); // $omod in selectDivScale()
1480 .addImm(0) in selectG_ICMP_or_FCMP()
1482 .addImm(0) in selectG_ICMP_or_FCMP()
1484 .addImm(0); // op_sel in selectG_ICMP_or_FCMP()
1538 SelectedMI.addImm(Src0Mods); in selectIntrinsicCmp()
1541 SelectedMI.addImm(Src1Mods); in selectIntrinsicCmp()
1544 SelectedMI.addImm(0); // clamp in selectIntrinsicCmp()
1546 SelectedMI.addImm(0); // op_sel in selectIntrinsicCmp()
1615 BuildMI(*BB, &I, DL, TII.get(Opcode), Dst).addImm(0); in selectBallot()
1644 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_MOV_B32), HiReg).addImm(0); in selectBallot()
1647 .addImm(AMDGPU::sub0) in selectBallot()
1649 .addImm(AMDGPU::sub1); in selectBallot()
1695 MIB.addImm(MFI->getLDSSize()); in selectGroupStaticSize()
1726 .addImm(0); in selectReturnAddress()
1822 .addImm(Offset) in selectDSOrderedIntrinsic()
1892 .addImm(0); in selectDSGWSIntrinsic()
1914 .addImm(16) in selectDSGWSIntrinsic()
1934 MIB.addImm(ImmOffset) in selectDSGWSIntrinsic()
1968 .addImm(Offset) in selectDSAppendConsume()
1969 .addImm(IsGDS ? -1 : 0) in selectDSAppendConsume()
2006 .addImm(AMDGPU::Barrier::WORKGROUP); in selectSBarrier()
2008 .addImm(AMDGPU::Barrier::WORKGROUP); in selectSBarrier()
2236 MIB.addImm(DMask); // dmask in selectImageIntrinsic()
2239 MIB.addImm(DimInfo->Encoding); in selectImageIntrinsic()
2241 MIB.addImm(Unorm); in selectImageIntrinsic()
2243 MIB.addImm(CPol); in selectImageIntrinsic()
2244 MIB.addImm(IsA16 && // a16 or r128 in selectImageIntrinsic()
2247 MIB.addImm(IsA16 ? -1 : 0); in selectImageIntrinsic()
2250 MIB.addImm(TFE); // tfe in selectImageIntrinsic()
2257 MIB.addImm(LWE); // lwe in selectImageIntrinsic()
2259 MIB.addImm(DimInfo->DA ? -1 : 0); in selectImageIntrinsic()
2261 MIB.addImm(IsD16 ? -1 : 0); in selectImageIntrinsic()
2303 .addImm(Offset) in selectDSBvhStackIntrinsic()
2414 .addImm(0) in selectG_SELECT()
2416 .addImm(0) in selectG_SELECT()
2488 .addImm(0) // $src0_modifiers in selectG_TRUNC()
2490 .addImm(0) // $clamp in selectG_TRUNC()
2491 .addImm(AMDGPU::SDWA::WORD_1) // $dst_sel in selectG_TRUNC()
2492 .addImm(AMDGPU::SDWA::UNUSED_PRESERVE) // $dst_unused in selectG_TRUNC()
2493 .addImm(AMDGPU::SDWA::WORD_0) // $src0_sel in selectG_TRUNC()
2502 .addImm(16) in selectG_TRUNC()
2507 .addImm(16) in selectG_TRUNC()
2516 .addImm(0xffff); in selectG_TRUNC()
2618 .addImm(AMDGPU::sub0) in selectG_SZA_EXT()
2620 .addImm(AMDGPU::sub1); in selectG_SZA_EXT()
2635 .addImm(Mask) in selectG_SZA_EXT()
2645 .addImm(0) // Offset in selectG_SZA_EXT()
2646 .addImm(SrcSize); // Width in selectG_SZA_EXT()
2674 .addImm(31) in selectG_SZA_EXT()
2678 .addImm(0); in selectG_SZA_EXT()
2682 .addImm(AMDGPU::sub0) in selectG_SZA_EXT()
2684 .addImm(AMDGPU::sub1); in selectG_SZA_EXT()
2703 .addImm(AMDGPU::sub0) in selectG_SZA_EXT()
2705 .addImm(AMDGPU::sub1); in selectG_SZA_EXT()
2709 .addImm(SrcSize << 16); in selectG_SZA_EXT()
2719 .addImm(Mask) in selectG_SZA_EXT()
2724 .addImm(SrcSize << 16); in selectG_SZA_EXT()
2843 .addImm(0x80000000); in selectG_FNEG()
2853 .addImm(AMDGPU::sub0) in selectG_FNEG()
2855 .addImm(AMDGPU::sub1); in selectG_FNEG()
2885 .addImm(0x7fffffff); in selectG_FABS()
2895 .addImm(AMDGPU::sub0) in selectG_FABS()
2897 .addImm(AMDGPU::sub1); in selectG_FABS()
2989 .addImm(-1); in initM0()
3195 .addImm(AMDGPU::sub0) in selectG_PTRMASK()
3197 .addImm(AMDGPU::sub1); in selectG_PTRMASK()
3299 .addImm(SubReg); in selectG_EXTRACT_VECTOR_ELT()
3362 .addImm(SubReg); in selectG_INSERT_VECTOR_ELT()
3373 .addImm(SubReg); in selectG_INSERT_VECTOR_ELT()
3451 .addImm(AMDGPU::sub0) in selectBufferLoadLds()
3453 .addImm(AMDGPU::sub1); in selectBufferLoadLds()
3467 MIB.addImm(Aux & (IsGFX12Plus ? AMDGPU::CPol::ALL in selectBufferLoadLds()
3469 MIB.addImm( in selectBufferLoadLds()
3578 .addImm(0); in selectGlobalLoadLds()
3757 .addImm(Subtarget->getWavefrontSizeLog2()) in selectWaveAddress()
3762 .addImm(Subtarget->getWavefrontSizeLog2()) in selectWaveAddress()
3958 MIB.addImm(0); // src_mod0 in selectBITOP3()
3961 MIB.addImm(0); // src_mod1 in selectBITOP3()
3964 MIB.addImm(0); // src_mod2 in selectBITOP3()
3966 .addImm(TTbl); in selectBITOP3()
3968 MIB.addImm(0); // op_sel in selectBITOP3()
3992 .addImm(Subtarget->getWavefrontSizeLog2()) in selectStackRestore()
4240 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods in selectVOP3Mods0()
4241 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp in selectVOP3Mods0()
4242 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod in selectVOP3Mods0()
4258 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods in selectVOP3BMods0()
4259 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp in selectVOP3BMods0()
4260 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod in selectVOP3BMods0()
4268 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp in selectVOP3OMods()
4269 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod in selectVOP3OMods()
4283 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3Mods()
4299 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3ModsNonCanonicalizing()
4315 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3BMods()
4891 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3PRetHelper()
4918 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3PModsNeg()
4932 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectWMMAOpSelVOP3PMods()
4959 MIB.addImm(SIRegisterInfo::getSubRegFromChannel(i)); in buildRegSequence()
5022 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }}}; in selectWMMAModsF32NegAbs()
5048 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }}}; in selectWMMAModsF16Neg()
5081 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }}}; in selectWMMAModsF16NegAbs()
5090 MIB.addImm(FPValReg->Value.bitcastToAPInt().getSExtValue()); in selectWMMAVISrc()
5102 {[=](MachineInstrBuilder &MIB) { MIB.addImm(ICst.getSExtValue()); }}}; in selectWMMAVISrc()
5126 [=](MachineInstrBuilder &MIB) { MIB.addImm(Key); } // index_key in selectSWMMACIndex8()
5148 [=](MachineInstrBuilder &MIB) { MIB.addImm(Key); } // index_key in selectSWMMACIndex16()
5161 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3OpSelMods()
5180 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods in selectVINTERPMods()
5198 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods in selectVINTERPModsHi()
5268 .addImm(GEPI.Imm); in selectSmrdOffset()
5291 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }}}; in selectSmrdImm()
5311 [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); } in selectSmrdImm32()
5334 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }}}; in selectSmrdSgprImm()
5369 [=](MachineInstrBuilder &MIB) { MIB.addImm(PtrWithOffset.second); }, in selectFlatOffset()
5379 [=](MachineInstrBuilder &MIB) { MIB.addImm(PtrWithOffset.second); }, in selectGlobalOffset()
5389 [=](MachineInstrBuilder &MIB) { MIB.addImm(PtrWithOffset.second); }, in selectScratchOffset()
5431 .addImm(RemainderOffset); in selectGlobalSAddr()
5438 [=](MachineInstrBuilder &MIB) { MIB.addImm(SplitImmOffset); }, in selectGlobalSAddr()
5477 MIB.addImm(ImmOffset); in selectGlobalSAddr()
5496 .addImm(0); in selectGlobalSAddr()
5501 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectGlobalSAddr()
5528 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectScratchSAddr()
5560 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectScratchSAddr()
5627 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectScratchSVAddr()
5637 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectScratchSVAddr()
5658 .addImm(Offset & ~MaxOffset); in selectMUBUFScratchOffen()
5669 MIB.addImm(0); in selectMUBUFScratchOffen()
5672 MIB.addImm(Offset & MaxOffset); in selectMUBUFScratchOffen()
5714 MIB.addImm(0); in selectMUBUFScratchOffen()
5717 MIB.addImm(Offset); in selectMUBUFScratchOffen()
5874 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // offset in selectMUBUFScratchOffset()
5899 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); } // offset in selectMUBUFScratchOffset()
5912 MIB.addImm(0); in selectMUBUFScratchOffset()
5914 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); } // offset in selectMUBUFScratchOffset()
5952 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); } in selectDS1Addr1Offset()
5974 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }, in selectDSReadWrite2()
5975 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset+1); } in selectDSReadWrite2()
6028 MIB.addImm(0); in addZeroImm()
6043 .addImm(FormatLo); in buildRSRC()
6046 .addImm(FormatHi); in buildRSRC()
6054 .addImm(AMDGPU::sub0) in buildRSRC()
6056 .addImm(AMDGPU::sub1); in buildRSRC()
6063 .addImm(0); in buildRSRC()
6069 .addImm(AMDGPU::sub0_sub1) in buildRSRC()
6071 .addImm(AMDGPU::sub2_sub3); in buildRSRC()
6148 .addImm(ImmOffset); in splitIllegalMUBUFOffset()
6253 MIB.addImm(0); in selectMUBUFAddr64()
6256 MIB.addImm(Offset); in selectMUBUFAddr64()
6283 MIB.addImm(0); in selectMUBUFOffset()
6285 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }, // offset in selectMUBUFOffset()
6325 return {{ [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); } }}; in selectSMRDBufferImm()
6341 return {{ [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); } }}; in selectSMRDBufferImm32()
6362 [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedOffset); }}}; in selectSMRDBufferSgprImm()
6429 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3PMadMixModsExt()
6442 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3PMadMixMods()
6453 BuildMI(*MBB, &I, DL, TII.get(AMDGPU::S_CMP_EQ_U32)).addImm(0).addImm(0); in selectSBarrierSignalIsfirst()
6456 .addImm(I.getOperand(2).getImm()); in selectSBarrierSignalIsfirst()
6490 MIB.addImm(*BarValImm); in selectSGetBarrierState()
6525 .addImm(4u) in selectNamedBarrierInit()
6531 .addImm(0x3F) in selectNamedBarrierInit()
6538 .addImm(0x3F) in selectNamedBarrierInit()
6545 .addImm(ShAmt) in selectNamedBarrierInit()
6580 .addImm(4u) in selectNamedBarrierInst()
6586 .addImm(0x3F) in selectNamedBarrierInst()
6609 MIB.addImm(BarId); in selectNamedBarrierInst()
6621 MIB.addImm(MI.getOperand(1).getCImm()->getSExtValue()); in renderTruncImm32()
6629 MIB.addImm(-MI.getOperand(1).getCImm()->getSExtValue()); in renderNegateImm()
6637 MIB.addImm(Op.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue()); in renderBitcastFPImm()
6645 MIB.addImm(MI.getOperand(1).getCImm()->getValue().popcount()); in renderPopcntImm()
6656 MIB.addImm(Imm); in renderTruncTImm()
6658 MIB.addImm(Op.getImm()); in renderTruncTImm()
6664 MIB.addImm(MI.getOperand(OpIdx).getImm() != 0); in renderZextBoolTImm()
6671 MIB.addImm(MI.getOperand(OpIdx).getImm() ? (int64_t)SISrcMods::OP_SEL_0 : 0); in renderOpSelTImm()
6677 MIB.addImm( in renderSrcAndDstSelToOpSelXForm_0_0()
6684 MIB.addImm((MI.getOperand(OpIdx).getImm() & 0x2) in renderSrcAndDstSelToOpSelXForm_0_1()
6692 MIB.addImm( in renderSrcAndDstSelToOpSelXForm_1_0()
6699 MIB.addImm((MI.getOperand(OpIdx).getImm() & 0x1) in renderSrcAndDstSelToOpSelXForm_1_1()
6707 MIB.addImm(MI.getOperand(OpIdx).getImm() ? (int64_t)(SISrcMods::DST_OP_SEL) in renderDstSelToOpSelXForm()
6714 MIB.addImm(MI.getOperand(OpIdx).getImm() ? (int64_t)(SISrcMods::OP_SEL_0) in renderSrcSelToOpSelXForm()
6721 MIB.addImm( in renderSrcAndDstSelToOpSelXForm_2_0()
6728 MIB.addImm( in renderDstSelToOpSel3XFormXForm()
6736 MIB.addImm(MI.getOperand(OpIdx).getImm() & in renderExtractCPol()
6748 MIB.addImm(Swizzle); in renderExtractSWZ()
6757 MIB.addImm(Cpol | AMDGPU::CPol::GLC); in renderExtractCpolSetGLC()
6772 MIB.addImm(ExpVal); in renderFPPow2ToExponent()
6782 MIB.addImm((MI.getOperand(OpIdx).getImm() + 3) % 4); in renderRoundMode()
6794 MIB.addImm(New); in renderScaledMAIIntrinsicOperand()