3330       Register SAddr =  in selectGlobalLoadLds()  local
3332       if (isSGPR(SAddr)) {  in selectGlobalLoadLds()
3335           Addr = SAddr;  in selectGlobalLoadLds()
4427     Register SAddr =  in selectGlobalSAddr()  local
4430     if (isSGPR(SAddr)) {  in selectGlobalSAddr()
4437                    MIB.addReg(SAddr);  in selectGlobalSAddr()
4498   Register SAddr = AddrDef->Reg;  in selectScratchSAddr()  local
4512       SAddr = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectScratchSAddr()
4514       BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_I32), SAddr)  in selectScratchSAddr()
4521   if (!isSGPR(SAddr))  in selectScratchSAddr()
4525       [=](MachineInstrBuilder &MIB) { MIB.addReg(SAddr); }, // saddr  in selectScratchSAddr()
4532     Register VAddr, Register SAddr, uint64_t ImmOffset) const {  in checkFlatScratchSVSSwizzleBug()  argument
4541       /*Add=*/true, /*NSW=*/false, /*NUW=*/false, KB->getKnownBits(SAddr),  in checkFlatScratchSVSSwizzleBug()