Lines Matching refs:DstBank
549 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_MERGE_VALUES() local
552 TRI.getRegClassForSizeOnBank(DstSize, *DstBank); in selectG_MERGE_VALUES()
644 const RegisterBank *DstBank = RBI.getRegBank(Dst, *MRI, TRI); in selectG_BUILD_VECTOR() local
645 if (DstBank->getID() == AMDGPU::AGPRRegBankID) in selectG_BUILD_VECTOR()
648 assert(DstBank->getID() == AMDGPU::SGPRRegBankID || in selectG_BUILD_VECTOR()
649 DstBank->getID() == AMDGPU::VGPRRegBankID); in selectG_BUILD_VECTOR()
650 const bool IsVector = DstBank->getID() == AMDGPU::VGPRRegBankID; in selectG_BUILD_VECTOR()
811 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_INSERT() local
813 TRI.getRegClassForSizeOnBank(DstSize, *DstBank); in selectG_INSERT()
1452 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectRelocConstant() local
1453 const TargetRegisterClass *DstRC = TRI.getRegClassForSizeOnBank(32, *DstBank); in selectRelocConstant()
1457 const bool IsVALU = DstBank->getID() == AMDGPU::VGPRRegBankID; in selectRelocConstant()
2366 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_SZA_EXT() local
2368 TRI.getRegClassForSizeOnBank(DstSize, *DstBank); in selectG_SZA_EXT()