Lines Matching +full:1 +full:mib
73 ? Def->getOperand(1).getReg() in getWaveAddress()
88 if (!Ty.isValid() || Ty.getSizeInBits() != 1) in isVCC()
102 MI.removeOperand(1); // Remove intrinsic ID. in constrainCopyLikeIntrin()
106 MachineOperand &Src = MI.getOperand(1); in constrainCopyLikeIntrin()
109 if (MRI->getType(Dst.getReg()) == LLT::scalar(1)) in constrainCopyLikeIntrin()
128 const MachineOperand &Src = I.getOperand(1); in selectCOPY()
156 .addImm(ConstVal->Value.getBoolValue() ? -1 : 0); in selectCOPY()
168 .addImm(1) in selectCOPY()
213 if (DefTy == LLT::scalar(1)) in selectPHI()
330 .add(I.getOperand(1)) in selectG_ADD_SUB()
351 .add(I.getOperand(1)) in selectG_ADD_SUB()
365 MachineOperand Lo1(getSubOperand64(I.getOperand(1), HalfRC, AMDGPU::sub0)); in selectG_ADD_SUB()
367 MachineOperand Hi1(getSubOperand64(I.getOperand(1), HalfRC, AMDGPU::sub1)); in selectG_ADD_SUB()
420 Register Dst1Reg = I.getOperand(1).getReg(); in selectG_UADDO_USUBO_UADDE_USUBE()
496 Register SrcReg = I.getOperand(1).getReg(); in selectG_EXTRACT()
529 *SrcRC, I.getOperand(1)); in selectG_EXTRACT()
542 LLT SrcTy = MRI->getType(MI.getOperand(1).getReg()); in selectG_MERGE_VALUES()
557 MachineInstrBuilder MIB = in selectG_MERGE_VALUES() local
559 for (int I = 0, E = MI.getNumOperands() - 1; I != E; ++I) { in selectG_MERGE_VALUES()
560 MachineOperand &Src = MI.getOperand(I + 1); in selectG_MERGE_VALUES()
561 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef())); in selectG_MERGE_VALUES()
562 MIB.addImm(SubRegs[I]); in selectG_MERGE_VALUES()
579 const int NumDst = MI.getNumOperands() - 1; in selectG_UNMERGE_VALUES()
626 Register Src0 = MI.getOperand(1).getReg(); in selectG_BUILD_VECTOR()
702 auto MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_AND_B32_e32), TmpReg) in selectG_BUILD_VECTOR() local
705 if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI)) in selectG_BUILD_VECTOR()
708 MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_LSHL_OR_B32_e64), Dst) in selectG_BUILD_VECTOR()
712 if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI)) in selectG_BUILD_VECTOR()
743 MI.getOperand(1).setReg(ShiftSrc0); in selectG_BUILD_VECTOR()
753 auto MIB = BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_LSHR_B32), Dst) in selectG_BUILD_VECTOR() local
759 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectG_BUILD_VECTOR()
763 MI.getOperand(1).setReg(ShiftSrc0); in selectG_BUILD_VECTOR()
790 Register Src0Reg = I.getOperand(1).getReg(); in selectG_INSERT()
847 Register SrcReg = MI.getOperand(1).getReg(); in selectG_SBFX_UBFX()
861 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), DstReg) in selectG_SBFX_UBFX() local
866 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectG_SBFX_UBFX()
917 // still required to abide by the 1 SGPR rule. Fix this up if we might have
921 if (STI.getConstantBusLimit(AMDGPU::V_WRITELANE_B32) > 1) in selectWritelane()
931 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::V_WRITELANE_B32), VDst); in selectWritelane() local
938 MIB.addReg(Val); in selectWritelane()
939 MIB.addImm(ConstSelect->Value.getSExtValue() & in selectWritelane()
949 MIB.addImm(ConstVal->Value.getSExtValue()); in selectWritelane()
950 MIB.addReg(LaneSelect); in selectWritelane()
952 MIB.addReg(Val); in selectWritelane()
959 BuildMI(*MBB, *MIB, DL, TII.get(AMDGPU::COPY), AMDGPU::M0) in selectWritelane()
961 MIB.addReg(AMDGPU::M0); in selectWritelane()
965 MIB.addReg(VDstIn); in selectWritelane()
968 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectWritelane()
975 Register Dst1 = MI.getOperand(1).getReg(); in selectDivScale()
997 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), Dst0) in selectDivScale() local
1009 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectDivScale()
1087 return -1; in getV_CMPOpcode()
1090 return -1; in getV_CMPOpcode()
1190 return -1; in getS_CMPOpcode()
1198 return -1; in getS_CMPOpcode()
1259 return -1; in getS_CMPOpcode()
1295 return -1; in getS_CMPOpcode()
1306 auto Pred = (CmpInst::Predicate)I.getOperand(1).getPredicate(); in selectG_ICMP_or_FCMP()
1311 if (Opcode == -1) in selectG_ICMP_or_FCMP()
1329 if (Opcode == -1) in selectG_ICMP_or_FCMP()
1358 if (Size == 1) in selectIntrinsicCmp()
1369 if (Opcode == -1) in selectIntrinsicCmp()
1439 } else if (Value == -1) // all ones in selectBallot()
1485 auto MIB = BuildMI(*MBB, &I, DL, TII.get(Mov), DstReg); in selectGroupStaticSize() local
1489 MIB.addImm(MFI->getLDSSize()); in selectGroupStaticSize()
1494 MIB.addGlobalAddress(GV, 0, SIInstrInfo::MO_ABS32_LO); in selectGroupStaticSize()
1498 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectGroupStaticSize()
1544 .add(MI.getOperand(1)); in selectEndCfIntrinsic()
1546 Register Reg = MI.getOperand(1).getReg(); in selectEndCfIntrinsic()
1575 if (CountDw < 1 || CountDw > 4) { in selectDSOrderedIntrinsic()
1577 "ds_ordered_count: dword count must be between 1 and 4"); in selectDSOrderedIntrinsic()
1584 unsigned Instruction = IntrID == Intrinsic::amdgcn_ds_ordered_add ? 0 : 1; in selectDSOrderedIntrinsic()
1588 unsigned Offset1 = WaveRelease | (WaveDone << 1) | (Instruction << 4); in selectDSOrderedIntrinsic()
1591 Offset1 |= (CountDw - 1) << 6; in selectDSOrderedIntrinsic()
1647 Register BaseOffset = MI.getOperand(HasVSrc ? 2 : 1).getReg(); in selectDSGWSIntrinsic()
1665 BaseOffset = OffsetDef->getOperand(1).getReg(); in selectDSGWSIntrinsic()
1672 // default -1 only set the low 16-bits, we could leave it as-is and add 1 to in selectDSGWSIntrinsic()
1675 ImmOffset = OffsetDef->getOperand(1).getCImm()->getZExtValue(); in selectDSGWSIntrinsic()
1688 Readfirstlane->getOperand(1).setReg(BaseOffset); in selectDSGWSIntrinsic()
1709 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(gwsIntrinToOpcode(IID))); in selectDSGWSIntrinsic() local
1712 Register VSrc = MI.getOperand(1).getReg(); in selectDSGWSIntrinsic()
1713 MIB.addReg(VSrc); in selectDSGWSIntrinsic()
1719 MIB.addImm(ImmOffset) in selectDSGWSIntrinsic()
1722 TII.enforceOperandRCAlignment(*MIB, AMDGPU::OpName::data0); in selectDSGWSIntrinsic()
1752 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), MI.getOperand(0).getReg()) in selectDSAppendConsume() local
1754 .addImm(IsGDS ? -1 : 0) in selectDSAppendConsume()
1757 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectDSAppendConsume()
1814 const unsigned ArgOffset = MI.getNumExplicitDefs() + 1; in selectImageIntrinsic()
1818 int NumVDataDwords = -1; in selectImageIntrinsic()
1836 const bool IsA16 = (Flags & 1) != 0; in selectImageIntrinsic()
1863 NumVDataDwords = Is64Bit ? 2 : 1; in selectImageIntrinsic()
1870 VDataIn = MI.getOperand(1).getReg(); in selectImageIntrinsic()
1881 NumVDataDwords = (DMaskLanes + 1) / 2; in selectImageIntrinsic()
1894 assert((!IsTexFail || DMaskLanes >= 1) && "should have legalized this"); in selectImageIntrinsic()
1923 NumVAddrRegs != 1 && in selectImageIntrinsic()
1934 int Opcode = -1; in selectImageIntrinsic()
1952 if (Opcode == -1) { in selectImageIntrinsic()
1959 if (Opcode == -1 && in selectImageIntrinsic()
1963 if (Opcode == -1) in selectImageIntrinsic()
1967 if (Opcode == -1) in selectImageIntrinsic()
1970 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opcode)) in selectImageIntrinsic() local
1981 MIB.addDef(TmpReg); in selectImageIntrinsic()
1988 MIB.addDef(VDataOut); // vdata output in selectImageIntrinsic()
1993 MIB.addReg(VDataIn); // vdata input in selectImageIntrinsic()
1999 MIB.addReg(SrcOp.getReg()); in selectImageIntrinsic()
2003 MIB.addReg(MI.getOperand(ArgOffset + Intr->RsrcIndex).getReg()); in selectImageIntrinsic()
2005 MIB.addReg(MI.getOperand(ArgOffset + Intr->SampIndex).getReg()); in selectImageIntrinsic()
2007 MIB.addImm(DMask); // dmask in selectImageIntrinsic()
2010 MIB.addImm(DimInfo->Encoding); in selectImageIntrinsic()
2012 MIB.addImm(Unorm); in selectImageIntrinsic()
2014 MIB.addImm(CPol); in selectImageIntrinsic()
2015 MIB.addImm(IsA16 && // a16 or r128 in selectImageIntrinsic()
2016 STI.hasFeature(AMDGPU::FeatureR128A16) ? -1 : 0); in selectImageIntrinsic()
2018 MIB.addImm(IsA16 ? -1 : 0); in selectImageIntrinsic()
2021 MIB.addImm(TFE); // tfe in selectImageIntrinsic()
2028 MIB.addImm(LWE); // lwe in selectImageIntrinsic()
2030 MIB.addImm(DimInfo->DA ? -1 : 0); in selectImageIntrinsic()
2032 MIB.addImm(IsD16 ? -1 : 0); in selectImageIntrinsic()
2035 constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectImageIntrinsic()
2036 TII.enforceOperandRCAlignment(*MIB, AMDGPU::OpName::vaddr); in selectImageIntrinsic()
2045 Register Dst1 = MI.getOperand(1).getReg(); in selectDSBvhStackIntrinsic()
2055 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::DS_BVH_STACK_RTN_B32), Dst0) in selectDSBvhStackIntrinsic() local
2064 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectDSBvhStackIntrinsic()
2131 const MachineOperand &CCOp = I.getOperand(1); in selectG_SELECT()
2165 .add(I.getOperand(1)); in selectG_SELECT()
2188 return -1; in sizeToSubRegIndex()
2195 Register SrcReg = I.getOperand(1).getReg(); in selectG_TRUNC()
2198 const LLT S1 = LLT::scalar(1); in selectG_TRUNC()
2253 MovSDWA->tieOperands(0, MovSDWA->getNumOperands() - 1); in selectG_TRUNC()
2297 if (SubRegIdx == -1) in selectG_TRUNC()
2312 I.getOperand(1).setSubReg(SubRegIdx); in selectG_TRUNC()
2346 const Register SrcReg = I.getOperand(1).getReg(); in selectG_SZA_EXT()
2510 Register Src = I.getOperand(1).getReg(); in selectG_FPEXT()
2528 MachineOperand &ImmOp = I.getOperand(1); in selectG_CONSTANT()
2551 AMDGPU::isValid32BitLiteral(I.getOperand(1).getImm(), IsFP)) { in selectG_CONSTANT()
2562 if (Size == 1) in selectG_CONSTANT()
2574 APInt Imm(Size, I.getOperand(1).getImm()); in selectG_CONSTANT()
2579 .addImm(I.getOperand(1).getImm()); in selectG_CONSTANT()
2627 Register Src = MI.getOperand(1).getReg(); in selectG_FNEG()
2630 Src = Fabs->getOperand(1).getReg(); in selectG_FNEG()
2673 Register Src = MI.getOperand(1).getReg(); in selectG_FABS()
2715 unsigned OpNo = Load.getOpcode() == AMDGPU::G_PREFETCH ? 0 : 1; in getAddrModeInfo()
2726 for (unsigned i = 1; i != 3; ++i) { in getAddrModeInfo()
2734 GEPInfo.Imm = OpDef->getOperand(1).getCImm()->getSExtValue(); in getAddrModeInfo()
2787 const LLT PtrTy = MRI->getType(I.getOperand(1).getReg()); in initM0()
2795 .addImm(-1); in initM0()
2813 return isVCmpResult(MI.getOperand(1).getReg(), MRI); in isVCmpResult()
2817 return isVCmpResult(MI.getOperand(1).getReg(), MRI) && in isVCmpResult()
2877 .addMBB(I.getOperand(1).getMBB()); in selectG_BRCOND()
2898 Register SrcReg = I.getOperand(1).getReg(); in selectG_PTRMASK()
2923 auto MIB = BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_AND_B64), DstReg) in selectG_PTRMASK() local
2928 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectG_PTRMASK()
2971 // If all the bits in the low half are 1, we only need a copy for it. in selectG_PTRMASK()
2986 // If all the bits in the high half are 1, we only need a copy for it. in selectG_PTRMASK()
3038 Register SrcReg = MI.getOperand(1).getReg(); in selectG_EXTRACT_VECTOR_ELT()
3115 Register VecReg = MI.getOperand(1).getReg(); in selectG_INSERT_VECTOR_ELT()
3196 OpOffset = 1; in selectBufferLoadLds()
3207 case 1: in selectBufferLoadLds()
3232 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc)); in selectBufferLoadLds() local
3236 BuildMI(*MBB, &*MIB, DL, TII.get(AMDGPU::REG_SEQUENCE), IdxReg) in selectBufferLoadLds()
3242 MIB.addReg(IdxReg); in selectBufferLoadLds()
3244 MIB.addReg(VIndex); in selectBufferLoadLds()
3246 MIB.addReg(VOffset); in selectBufferLoadLds()
3249 MIB.add(MI.getOperand(1)); // rsrc in selectBufferLoadLds()
3250 MIB.add(MI.getOperand(5 + OpOffset)); // soffset in selectBufferLoadLds()
3251 MIB.add(MI.getOperand(6 + OpOffset)); // imm offset in selectBufferLoadLds()
3253 MIB.addImm(Aux & AMDGPU::CPol::ALL); // cpol in selectBufferLoadLds()
3254 MIB.addImm(Aux & AMDGPU::CPol::SWZ_pregfx12 ? 1 : 0); // swz in selectBufferLoadLds()
3272 MIB.setMemRefs({LoadMMO, StoreMMO}); in selectBufferLoadLds()
3275 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectBufferLoadLds()
3292 return Def->getOperand(1).getReg(); in matchZeroExtendFromS32()
3305 case 1: in selectGlobalLoadLds()
3321 Register Addr = MI.getOperand(1).getReg(); in selectGlobalLoadLds()
3331 getSrcRegIgnoringCopies(AddrDef->MI->getOperand(1).getReg(), *MRI); in selectGlobalLoadLds()
3351 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc)) in selectGlobalLoadLds() local
3355 MIB.addReg(VOffset); in selectGlobalLoadLds()
3357 MIB.add(MI.getOperand(4)) // offset in selectGlobalLoadLds()
3374 MIB.setMemRefs({LoadMMO, StoreMMO}); in selectGlobalLoadLds()
3377 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectGlobalLoadLds()
3381 MI.setDesc(TII.get(MI.getOperand(1).getImm())); in selectBVHIntrinsic()
3382 MI.removeOperand(1); in selectBVHIntrinsic()
3440 MI.removeOperand(1); // Intrinsic ID in selectSMFMACIntrin()
3448 Register SrcReg = MI.getOperand(1).getReg(); in selectWaveAddress()
3601 if (MRI->getType(I.getOperand(1).getReg()) != LLT::scalar(1) && in select()
3652 [=](MachineInstrBuilder &MIB) { MIB.add(Root); } in selectVCSRC()
3666 Src = MI->getOperand(1).getReg(); in selectVOP3ModsImpl()
3673 getConstantFPVRegVal(MI->getOperand(1).getReg(), *MRI); in selectVOP3ModsImpl()
3681 Src = MI->getOperand(1).getReg(); in selectVOP3ModsImpl()
3716 [=](MachineInstrBuilder &MIB) { MIB.add(Root); } in selectVSRC0()
3727 [=](MachineInstrBuilder &MIB) { in selectVOP3Mods0()
3728 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB)); in selectVOP3Mods0()
3730 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods in selectVOP3Mods0()
3731 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp in selectVOP3Mods0()
3732 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod in selectVOP3Mods0()
3745 [=](MachineInstrBuilder &MIB) { in selectVOP3BMods0()
3746 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB)); in selectVOP3BMods0()
3748 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods in selectVOP3BMods0()
3749 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp in selectVOP3BMods0()
3750 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod in selectVOP3BMods0()
3757 [=](MachineInstrBuilder &MIB) { MIB.add(Root); }, in selectVOP3OMods()
3758 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp in selectVOP3OMods()
3759 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod in selectVOP3OMods()
3770 [=](MachineInstrBuilder &MIB) { in selectVOP3Mods()
3771 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB)); in selectVOP3Mods()
3773 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3Mods()
3785 [=](MachineInstrBuilder &MIB) { in selectVOP3ModsNonCanonicalizing()
3786 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB)); in selectVOP3ModsNonCanonicalizing()
3788 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3ModsNonCanonicalizing()
3800 [=](MachineInstrBuilder &MIB) { in selectVOP3BMods()
3801 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB)); in selectVOP3BMods()
3803 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3BMods()
3814 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); }, in selectVOP3NoMods()
3829 Src = MI->getOperand(1).getReg(); in selectVOP3PModsImpl()
3854 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3PMods()
3855 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3PMods()
3869 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3PModsDOT()
3870 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3PModsDOT()
3878 // 1(-1) promotes packed values to signed, 0 treats them as unsigned. in selectVOP3PModsNeg()
3879 assert((Root.isImm() && (Root.getImm() == -1 || Root.getImm() == 0)) && in selectVOP3PModsNeg()
3882 if (Root.getImm() == -1) in selectVOP3PModsNeg()
3885 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3PModsNeg()
3892 assert((Root.isImm() && (Root.getImm() == -1 || Root.getImm() == 0)) && in selectWMMAOpSelVOP3PMods()
3899 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectWMMAOpSelVOP3PMods()
3922 auto MIB = B.buildInstr(AMDGPU::REG_SEQUENCE) in buildRegSequence() local
3925 MIB.addReg(Elts[i]); in buildRegSequence()
3926 MIB.addImm(SIRegisterInfo::getSubRegFromChannel(i)); in buildRegSequence()
3928 return MIB->getOperand(0).getReg(); in buildRegSequence()
3978 EltsF32.push_back(ElF32->getOperand(1).getReg()); in selectWMMAModsF32NegAbs()
3988 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectWMMAModsF32NegAbs()
3989 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }}}; in selectWMMAModsF32NegAbs()
4014 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectWMMAModsF16Neg()
4015 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }}}; in selectWMMAModsF16Neg()
4036 EltsV2F16.push_back(ElV2F16->getOperand(1).getReg()); in selectWMMAModsF16NegAbs()
4047 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectWMMAModsF16NegAbs()
4048 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }}}; in selectWMMAModsF16NegAbs()
4056 return {{[=](MachineInstrBuilder &MIB) { in selectWMMAVISrc()
4057 MIB.addImm(FPValReg->Value.bitcastToAPInt().getSExtValue()); in selectWMMAVISrc()
4069 {[=](MachineInstrBuilder &MIB) { MIB.addImm(ICst.getSExtValue()); }}}; in selectWMMAVISrc()
4092 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectSWMMACIndex8()
4093 [=](MachineInstrBuilder &MIB) { MIB.addImm(Key); } // index_key in selectSWMMACIndex8()
4110 Key = 1; in selectSWMMACIndex16()
4114 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectSWMMACIndex16()
4115 [=](MachineInstrBuilder &MIB) { MIB.addImm(Key); } // index_key in selectSWMMACIndex16()
4127 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3OpSelMods()
4128 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3OpSelMods()
4142 [=](MachineInstrBuilder &MIB) { in selectVINTERPMods()
4143 MIB.addReg( in selectVINTERPMods()
4144 copyToVGPRIfSrcFolded(Src, Mods, Root, MIB, /* ForceVGPR */ true)); in selectVINTERPMods()
4146 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods in selectVINTERPMods()
4160 [=](MachineInstrBuilder &MIB) { in selectVINTERPModsHi()
4161 MIB.addReg( in selectVINTERPModsHi()
4162 copyToVGPRIfSrcFolded(Src, Mods, Root, MIB, /* ForceVGPR */ true)); in selectVINTERPModsHi()
4164 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods in selectVINTERPModsHi()
4189 if (GEPI.SgprParts.size() == 1 && GEPI.Imm != 0 && EncodedImm && in selectSmrdOffset()
4190 AddrInfo.size() > 1) { in selectSmrdOffset()
4191 const GEPInfo &GEPI2 = AddrInfo[1]; in selectSmrdOffset()
4194 matchZeroExtendFromS32(*MRI, GEPI2.SgprParts[1])) { in selectSmrdOffset()
4218 if (Offset && GEPI.SgprParts.size() == 1 && EncodedImm) { in selectSmrdOffset()
4225 if (SOffset && GEPI.SgprParts.size() == 1 && isUInt<32>(GEPI.Imm) && in selectSmrdOffset()
4239 if (Register OffsetReg = matchZeroExtendFromS32(*MRI, GEPI.SgprParts[1])) { in selectSmrdOffset()
4256 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); }, in selectSmrdImm()
4257 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }}}; in selectSmrdImm()
4265 if (AddrInfo.empty() || AddrInfo[0].SgprParts.size() != 1) in selectSmrdImm32()
4276 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdImm32()
4277 [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); } in selectSmrdImm32()
4287 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); }, in selectSmrdSgpr()
4288 [=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }}}; in selectSmrdSgpr()
4298 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); }, in selectSmrdSgprImm()
4299 [=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }, in selectSmrdSgprImm()
4300 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }}}; in selectSmrdSgprImm()
4334 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, in selectFlatOffset()
4335 [=](MachineInstrBuilder &MIB) { MIB.addImm(PtrWithOffset.second); }, in selectFlatOffset()
4344 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, in selectGlobalOffset()
4345 [=](MachineInstrBuilder &MIB) { MIB.addImm(PtrWithOffset.second); }, in selectGlobalOffset()
4354 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, in selectScratchOffset()
4355 [=](MachineInstrBuilder &MIB) { MIB.addImm(PtrWithOffset.second); }, in selectScratchOffset()
4400 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrBase); }, // saddr in selectGlobalSAddr()
4401 [=](MachineInstrBuilder &MIB) { in selectGlobalSAddr()
4402 MIB.addReg(HighBits); in selectGlobalSAddr()
4404 [=](MachineInstrBuilder &MIB) { MIB.addImm(SplitImmOffset); }, in selectGlobalSAddr()
4410 // is 1 we would need to perform 1 or 2 extra moves for each half of in selectGlobalSAddr()
4428 getSrcRegIgnoringCopies(AddrDef->MI->getOperand(1).getReg(), *MRI); in selectGlobalSAddr()
4436 return {{[=](MachineInstrBuilder &MIB) { // saddr in selectGlobalSAddr()
4437 MIB.addReg(SAddr); in selectGlobalSAddr()
4439 [=](MachineInstrBuilder &MIB) { // voffset in selectGlobalSAddr()
4440 MIB.addReg(VOffset); in selectGlobalSAddr()
4442 [=](MachineInstrBuilder &MIB) { // offset in selectGlobalSAddr()
4443 MIB.addImm(ImmOffset); in selectGlobalSAddr()
4465 [=](MachineInstrBuilder &MIB) { MIB.addReg(AddrDef->Reg); }, // saddr in selectGlobalSAddr()
4466 [=](MachineInstrBuilder &MIB) { MIB.addReg(VOffset); }, // voffset in selectGlobalSAddr()
4467 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectGlobalSAddr()
4491 int FI = AddrDef->MI->getOperand(1).getIndex(); in selectScratchSAddr()
4493 [=](MachineInstrBuilder &MIB) { MIB.addFrameIndex(FI); }, // saddr in selectScratchSAddr()
4494 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectScratchSAddr()
4501 Register LHS = AddrDef->MI->getOperand(1).getReg(); in selectScratchSAddr()
4508 int FI = LHSDef->MI->getOperand(1).getIndex(); in selectScratchSAddr()
4525 [=](MachineInstrBuilder &MIB) { MIB.addReg(SAddr); }, // saddr in selectScratchSAddr()
4526 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectScratchSAddr()
4537 // from the two low order bits (i.e. from bit 1 into bit 2) when adding in checkFlatScratchSVSSwizzleBug()
4574 Register LHS = AddrDef->MI->getOperand(1).getReg(); in selectScratchSVAddr()
4589 int FI = LHSDef->MI->getOperand(1).getIndex(); in selectScratchSVAddr()
4591 [=](MachineInstrBuilder &MIB) { MIB.addReg(RHS); }, // vaddr in selectScratchSVAddr()
4592 [=](MachineInstrBuilder &MIB) { MIB.addFrameIndex(FI); }, // saddr in selectScratchSVAddr()
4593 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectScratchSVAddr()
4601 [=](MachineInstrBuilder &MIB) { MIB.addReg(RHS); }, // vaddr in selectScratchSVAddr()
4602 [=](MachineInstrBuilder &MIB) { MIB.addReg(LHS); }, // saddr in selectScratchSVAddr()
4603 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectScratchSVAddr()
4626 return {{[=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFScratchOffen()
4627 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffen()
4629 [=](MachineInstrBuilder &MIB) { // vaddr in selectMUBUFScratchOffen()
4630 MIB.addReg(HighBits); in selectMUBUFScratchOffen()
4632 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFScratchOffen()
4635 MIB.addImm(0); in selectMUBUFScratchOffen()
4637 [=](MachineInstrBuilder &MIB) { // offset in selectMUBUFScratchOffen()
4638 MIB.addImm(Offset & MaxOffset); in selectMUBUFScratchOffen()
4642 assert(Offset == 0 || Offset == -1); in selectMUBUFScratchOffen()
4658 FI = PtrBaseDef->getOperand(1).getIndex(); in selectMUBUFScratchOffen()
4664 FI = RootDef->getOperand(1).getIndex(); in selectMUBUFScratchOffen()
4668 return {{[=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFScratchOffen()
4669 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffen()
4671 [=](MachineInstrBuilder &MIB) { // vaddr in selectMUBUFScratchOffen()
4673 MIB.addFrameIndex(*FI); in selectMUBUFScratchOffen()
4675 MIB.addReg(VAddr); in selectMUBUFScratchOffen()
4677 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFScratchOffen()
4680 MIB.addImm(0); in selectMUBUFScratchOffen()
4682 [=](MachineInstrBuilder &MIB) { // offset in selectMUBUFScratchOffen()
4683 MIB.addImm(Offset); in selectMUBUFScratchOffen()
4737 Register LHS = AddrMI->getOperand(1).getReg(); in isFlatScratchBaseLegal()
4768 Register LHS = AddrMI->getOperand(1).getReg(); in isFlatScratchBaseLegalSV()
4783 Register Base = AddrMI->getOperand(1).getReg(); in isFlatScratchBaseLegalSVImm()
4800 Register LHS = BaseDef->MI->getOperand(1).getReg(); in isFlatScratchBaseLegalSVImm()
4817 const APInt &LHSKnownZeros = KB->getKnownZeroes(MI.getOperand(1).getReg()); in isUnneededShiftMask()
4834 [=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFScratchOffset()
4835 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffset()
4837 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFScratchOffset()
4838 MIB.addReg(WaveBase); in selectMUBUFScratchOffset()
4840 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // offset in selectMUBUFScratchOffset()
4859 [=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFScratchOffset()
4860 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffset()
4862 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFScratchOffset()
4863 MIB.addReg(WaveBase); in selectMUBUFScratchOffset()
4865 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); } // offset in selectMUBUFScratchOffset()
4874 [=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFScratchOffset()
4875 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffset()
4877 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFScratchOffset()
4878 MIB.addImm(0); in selectMUBUFScratchOffset()
4880 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); } // offset in selectMUBUFScratchOffset()
4920 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); }, in selectDS1Addr1Offset()
4921 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); } in selectDS1Addr1Offset()
4942 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); }, in selectDSReadWrite2()
4943 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }, in selectDSReadWrite2()
4944 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset+1); } in selectDSReadWrite2()
4996 return {RootI->getOperand(1).getReg(), MaybeOffset->Value.getSExtValue()}; in getPtrBaseWithConstantOffset()
4999 static void addZeroImm(MachineInstrBuilder &MIB) { in addZeroImm() argument
5000 MIB.addImm(0); in addZeroImm()
5063 return buildRSRC(B, MRI, -1, Hi_32(DefaultFormat), BasePtr); in buildOffsetSrc()
5082 Data.N2 = InputAdd->getOperand(1).getReg(); in parseMUBUFAddress()
5213 [=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFAddr64()
5214 MIB.addReg(RSrcReg); in selectMUBUFAddr64()
5216 [=](MachineInstrBuilder &MIB) { // vaddr in selectMUBUFAddr64()
5217 MIB.addReg(VAddr); in selectMUBUFAddr64()
5219 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFAddr64()
5221 MIB.addReg(SOffset); in selectMUBUFAddr64()
5223 MIB.addReg(AMDGPU::SGPR_NULL); in selectMUBUFAddr64()
5225 MIB.addImm(0); in selectMUBUFAddr64()
5227 [=](MachineInstrBuilder &MIB) { // offset in selectMUBUFAddr64()
5228 MIB.addImm(Offset); in selectMUBUFAddr64()
5246 [=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFOffset()
5247 MIB.addReg(RSrcReg); in selectMUBUFOffset()
5249 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFOffset()
5251 MIB.addReg(SOffset); in selectMUBUFOffset()
5253 MIB.addReg(AMDGPU::SGPR_NULL); in selectMUBUFOffset()
5255 MIB.addImm(0); in selectMUBUFOffset()
5257 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }, // offset in selectMUBUFOffset()
5272 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }}}; in selectBUFSOffset()
5296 return {{ [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); } }}; in selectSMRDBufferImm()
5312 return {{ [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); } }}; in selectSMRDBufferImm32()
5332 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }, in selectSMRDBufferSgprImm()
5333 [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedOffset); }}}; in selectSMRDBufferSgprImm()
5340 return getDefIgnoringCopies(MI->getOperand(1).getReg(), MRI); in stripBitCast()
5354 getDefIgnoringCopies(Inst->getOperand(1).getReg(), MRI); in isExtractHiElt()
5363 getDefIgnoringCopies(TruncOp->getOperand(1).getReg(), MRI); in isExtractHiElt()
5368 // G_SHUFFLE_VECTOR x, y, shufflemask(1, 1|0) in isExtractHiElt()
5369 // 1, 0 swaps the low/high 16 bits. in isExtractHiElt()
5370 // 1, 1 sets the high 16 bits to be the same as the low 16. in isExtractHiElt()
5379 if (Mask[0] == 1 && Mask[1] <= 1) { in isExtractHiElt()
5381 getDefIgnoringCopies(TruncOp->getOperand(1).getReg(), MRI); in isExtractHiElt()
5400 MachineOperand *MO = &MI->getOperand(1); in selectVOP3PMadMixModsImpl()
5409 MO = &MI->getOperand(1); in selectVOP3PMadMixModsImpl()
5465 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3PMadMixModsExt()
5466 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3PMadMixModsExt()
5478 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3PMadMixMods()
5479 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3PMadMixMods()
5545 : I.getOperand(1); in selectNamedBarrierInst()
5586 MachineInstrBuilder MIB; in selectNamedBarrierInst() local
5588 MIB = BuildMI(*MBB, &I, DL, TII.get(Opc)); in selectNamedBarrierInst()
5591 MIB.addDef(I.getOperand(0).getReg()); in selectNamedBarrierInst()
5594 MIB.addImm(*BarValImm); in selectNamedBarrierInst()
5613 void AMDGPUInstructionSelector::renderTruncImm32(MachineInstrBuilder &MIB, in renderTruncImm32() argument
5616 assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 && in renderTruncImm32()
5618 MIB.addImm(MI.getOperand(1).getCImm()->getSExtValue()); in renderTruncImm32()
5621 void AMDGPUInstructionSelector::renderNegateImm(MachineInstrBuilder &MIB, in renderNegateImm() argument
5624 assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 && in renderNegateImm()
5626 MIB.addImm(-MI.getOperand(1).getCImm()->getSExtValue()); in renderNegateImm()
5629 void AMDGPUInstructionSelector::renderBitcastImm(MachineInstrBuilder &MIB, in renderBitcastImm() argument
5632 assert(OpIdx == -1); in renderBitcastImm()
5634 const MachineOperand &Op = MI.getOperand(1); in renderBitcastImm()
5636 MIB.addImm(Op.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue()); in renderBitcastImm()
5639 MIB.addImm(Op.getCImm()->getSExtValue()); in renderBitcastImm()
5643 void AMDGPUInstructionSelector::renderPopcntImm(MachineInstrBuilder &MIB, in renderPopcntImm() argument
5646 assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 && in renderPopcntImm()
5648 MIB.addImm(MI.getOperand(1).getCImm()->getValue().popcount()); in renderPopcntImm()
5653 void AMDGPUInstructionSelector::renderTruncTImm(MachineInstrBuilder &MIB, in renderTruncTImm() argument
5656 MIB.addImm(MI.getOperand(OpIdx).getImm()); in renderTruncTImm()
5659 void AMDGPUInstructionSelector::renderOpSelTImm(MachineInstrBuilder &MIB, in renderOpSelTImm() argument
5663 MIB.addImm(MI.getOperand(OpIdx).getImm() ? (int64_t)SISrcMods::OP_SEL_0 : 0); in renderOpSelTImm()
5666 void AMDGPUInstructionSelector::renderExtractCPol(MachineInstrBuilder &MIB, in renderExtractCPol() argument
5670 MIB.addImm(MI.getOperand(OpIdx).getImm() & in renderExtractCPol()
5675 void AMDGPUInstructionSelector::renderExtractSWZ(MachineInstrBuilder &MIB, in renderExtractSWZ() argument
5682 MIB.addImm(Swizzle); in renderExtractSWZ()
5686 MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const { in renderExtractCpolSetGLC() argument
5691 MIB.addImm(Cpol | AMDGPU::CPol::GLC); in renderExtractCpolSetGLC()
5694 void AMDGPUInstructionSelector::renderFrameIndex(MachineInstrBuilder &MIB, in renderFrameIndex() argument
5697 MIB.addFrameIndex(MI.getOperand(1).getIndex()); in renderFrameIndex()
5700 void AMDGPUInstructionSelector::renderFPPow2ToExponent(MachineInstrBuilder &MIB, in renderFPPow2ToExponent() argument
5703 const APFloat &APF = MI.getOperand(1).getFPImm()->getValueAPF(); in renderFPPow2ToExponent()
5706 MIB.addImm(ExpVal); in renderFPPow2ToExponent()