Lines Matching full:src1

208 // out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
211 // out = (src1 > src0) ? 1 : 0
248 //  src1 = Denominator, src2 = Numerator).
253 // Special case divide fixup and flags(src0 = Quotient, src1 =
273 // src1: dst - rat offset (aka pointer) in dwords
350   SDTCisSameAs<3, 2>, // f32 src1
422 def AMDGPUfp_class : PatFrags<(ops node:$src0, node:$src1),
423   [(int_amdgcn_class node:$src0, node:$src1),
424    (AMDGPUfp_class_impl node:$src0, node:$src1)]>;
426 def AMDGPUfmed3 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
427   [(int_amdgcn_fmed3 node:$src0, node:$src1, node:$src2),
428    (AMDGPUfmed3_impl node:$src0, node:$src1, node:$src2)]>;
430 def AMDGPUdiv_fixup : PatFrags<(ops node:$src0, node:$src1, node:$src2),
431   [(int_amdgcn_div_fixup node:$src0, node:$src1, node:$src2),
432    (AMDGPUdiv_fixup_impl node:$src0, node:$src1, node:$src2)]>;
446 def AMDGPUpkrtz_f16_f32 : PatFrags<(ops node:$src0, node:$src1),
447   [(int_amdgcn_cvt_pkrtz node:$src0, node:$src1),
448   (AMDGPUpkrtz_f16_f32_impl node:$src0, node:$src1)]>;
450 def AMDGPUpknorm_i16_f32 : PatFrags<(ops node:$src0, node:$src1),
451   [(int_amdgcn_cvt_pknorm_i16 node:$src0, node:$src1),
452   (AMDGPUpknorm_i16_f32_impl node:$src0, node:$src1)]>;
454 def AMDGPUpknorm_u16_f32 : PatFrags<(ops node:$src0, node:$src1),
455   [(int_amdgcn_cvt_pknorm_u16 node:$src0, node:$src1),
456   (AMDGPUpknorm_u16_f32_impl node:$src0, node:$src1)]>;
458 def AMDGPUpk_i16_i32 : PatFrags<(ops node:$src0, node:$src1),
459   [(int_amdgcn_cvt_pk_i16 node:$src0, node:$src1),
460   (AMDGPUpk_i16_i32_impl node:$src0, node:$src1)]>;
462 def AMDGPUpk_u16_u32 : PatFrags<(ops node:$src0, node:$src1),
463   [(int_amdgcn_cvt_pk_u16 node:$src0, node:$src1),
464   (AMDGPUpk_u16_u32_impl node:$src0, node:$src1)]>;
466 def AMDGPUfmad_ftz : PatFrags<(ops node:$src0, node:$src1, node:$src2),
467   [(int_amdgcn_fmad_ftz node:$src0, node:$src1, node:$src2),
468    (AMDGPUfmad_ftz_impl node:$src0, node:$src1, node:$src2)]>;
470 def AMDGPUmul_u24 : PatFrags<(ops node:$src0, node:$src1),
471   [(int_amdgcn_mul_u24 node:$src0, node:$src1),
472    (AMDGPUmul_u24_impl node:$src0, node:$src1)]>;
474 def AMDGPUmul_i24 : PatFrags<(ops node:$src0, node:$src1),
475   [(int_amdgcn_mul_i24 node:$src0, node:$src1),
476    (AMDGPUmul_i24_impl node:$src0, node:$src1)]>;
478 def AMDGPUmulhi_u24 : PatFrags<(ops node:$src0, node:$src1),
479   [(int_amdgcn_mulhi_u24 node:$src0, node:$src1),
480    (AMDGPUmulhi_u24_impl node:$src0, node:$src1)]>;
482 def AMDGPUmulhi_i24 : PatFrags<(ops node:$src0, node:$src1),
483   [(int_amdgcn_mulhi_i24 node:$src0, node:$src1),
484    (AMDGPUmulhi_i24_impl node:$src0, node:$src1)]>;
486 def AMDGPUbfe_i32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
487   [(int_amdgcn_sbfe node:$src0, node:$src1, node:$src2),
488    (AMDGPUbfe_i32_impl node:$src0, node:$src1, node:$src2)]>;
490 def AMDGPUbfe_u32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
491   [(int_amdgcn_ubfe node:$src0, node:$src1, node:$src2),
492    (AMDGPUbfe_u32_impl node:$src0, node:$src1, node:$src2)]>;
494 def AMDGPUfmul_legacy : PatFrags<(ops node:$src0, node:$src1),
495   [(int_amdgcn_fmul_legacy node:$src0, node:$src1),
496    (AMDGPUfmul_legacy_impl node:$src0, node:$src1)]>;
498 def AMDGPUfdot2 : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$clamp),
499   [(int_amdgcn_fdot2 node:$src0, node:$src1, node:$src2, node:$clamp),
500    (AMDGPUfdot2_impl node:$src0, node:$src1, node:$src2, node:$clamp)]>;
502 def AMDGPUdiv_fmas : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$vcc),
503   [(int_amdgcn_div_fmas node:$src0, node:$src1, node:$src2, node:$vcc),
504    (AMDGPUdiv_fmas_impl node:$src0, node:$src1, node:$src2, node:$vcc)]>;
506 def AMDGPUperm : PatFrags<(ops node:$src0, node:$src1, node:$src2),
507   [(int_amdgcn_perm node:$src0, node:$src1, node:$src2),
508    (AMDGPUperm_impl node:$src0, node:$src1, node:$src2)]>;