Lines Matching +full:src +full:- +full:2
1 //===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
21 def AMDGPUFPClassOp : SDTypeProfile<1, 2,
22 [SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>]
25 def AMDGPUFPPackOp : SDTypeProfile<1, 2,
26 [SDTCisFP<1>, SDTCisSameAs<1, 2>]
29 def AMDGPUIntPackOp : SDTypeProfile<1, 2,
30 [SDTCisInt<1>, SDTCisSameAs<1, 2>]
33 def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
34 [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
39 [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>]
45 def AMDGPUIfOp : SDTypeProfile<1, 2,
46 [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, OtherVT>]
49 def AMDGPUElseOp : SDTypeProfile<1, 2,
50 [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, OtherVT>]
53 def AMDGPULoopOp : SDTypeProfile<0, 2,
57 def AMDGPUIfBreakOp : SDTypeProfile<1, 2,
58 [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, i1>]
61 //===----------------------------------------------------------------------===//
80 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
98 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
103 SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>,
117 // out = a - floor(a)
136 // out = 1.0 / sqrt(a) result clamped to +/- max_float.
151 // x < nan ? x : nan -> nan
152 // nan < x ? nan : x -> x
167 // than 2 operands.
215 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
238 // urecip - This operation is a helper for integer division, it returns the
240 // out = (2^32 / a) + e
260 SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
264 SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
268 // 8-bit and 16-bit values. The definition is:
270 // MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
272 // src0: vec4(src, 0, 0, mask)
273 // src1: dst - rat offset (aka pointer) in dwords
275 SDTypeProfile<0, 2, []>,
279 SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisVec<2>]>,
293 // Signed and unsigned 24-bit multiply. The highest 8-bits are ignore
295 def AMDGPUMul24Op : SDTypeProfile<1, 2, [
296 SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 2>
306 // mulhi24 yields the high-order 16 bits of the 48-bit result. Here's an example
338 SDTypeProfile<1, 4, [SDTCisSameAs<0, 3>, SDTCisSameAs<1, 2>,
350 SDTCisSameAs<3, 2>, // f32 src1
351 SDTCisSameAs<4, 2>, // f32 src2
352 SDTCisSameAs<5, 2>, // f32 src3
360 //===----------------------------------------------------------------------===//
362 //===----------------------------------------------------------------------===//
364 def SDTIL_BRCond : SDTypeProfile<0, 2, [
368 //===----------------------------------------------------------------------===//
370 //===----------------------------------------------------------------------===//
373 //===----------------------------------------------------------------------===//
375 //===----------------------------------------------------------------------===//
391 //===----------------------------------------------------------------------===//
393 //===----------------------------------------------------------------------===//
395 def AMDGPUrcp : PatFrags<(ops node:$src), [(int_amdgcn_rcp node:$src),
396 (AMDGPUrcp_impl node:$src)]>;
397 def AMDGPUrcp_legacy : PatFrags<(ops node:$src), [(int_amdgcn_rcp_legacy node:$src),
398 (AMDGPUrcp_legacy_impl node:$src)]>;
400 def AMDGPUrsq : PatFrags<(ops node:$src), [(int_amdgcn_rsq node:$src),
401 (AMDGPUrsq_impl node:$src)]>;
403 def AMDGPUrsq_clamp : PatFrags<(ops node:$src), [(int_amdgcn_rsq_clamp node:$src),
404 (AMDGPUrsq_clamp_impl node:$src)]>;
406 def AMDGPUsin : PatFrags<(ops node:$src), [(int_amdgcn_sin node:$src),
407 (AMDGPUsin_impl node:$src)]>;
408 def AMDGPUcos : PatFrags<(ops node:$src), [(int_amdgcn_cos node:$src),
409 (AMDGPUcos_impl node:$src)]>;
410 def AMDGPUfract : PatFrags<(ops node:$src), [(int_amdgcn_fract node:$src),
411 (AMDGPUfract_impl node:$src)]>;
412 def AMDGPUlog : PatFrags<(ops node:$src), [(int_amdgcn_log node:$src),
413 (AMDGPUlog_impl node:$src)]>;
414 def AMDGPUlogf16 : PatFrags<(ops node:$src), [(int_amdgcn_log node:$src),
415 (flog2 node:$src)]>;
417 def AMDGPUexp : PatFrags<(ops node:$src), [(int_amdgcn_exp2 node:$src),
418 (AMDGPUexp_impl node:$src)]>;
419 def AMDGPUexpf16 : PatFrags<(ops node:$src), [(int_amdgcn_exp2 node:$src),
420 (fexp2 node:$src)]>;
434 def AMDGPUffbh_i32 : PatFrags<(ops node:$src),
435 [(int_amdgcn_sffbh node:$src),
436 (AMDGPUffbh_i32_impl node:$src)]>;
438 def AMDGPUffbh_u32 : PatFrags<(ops node:$src),
439 [(ctlz_zero_undef node:$src),
440 (AMDGPUffbh_u32_impl node:$src)]>;
442 def AMDGPUffbl_b32 : PatFrags<(ops node:$src),
443 [(cttz_zero_undef node:$src),
444 (AMDGPUffbl_b32_impl node:$src)]>;