Lines Matching refs:SDLoc
35 SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
71 const SDLoc SL, SDValue Op,
77 SDValue LowerFLOGUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
81 SDValue lowerFEXPUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
83 SDValue lowerFEXP10Unsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
109 SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
120 SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
154 std::pair<SDValue, SDValue> splitVector(const SDValue &N, const SDLoc &DL,
252 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
273 SDValue combineFMinMaxLegacyImpl(const SDLoc &DL, EVT VT, SDValue LHS,
277 SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
340 const SDLoc &SL,
345 return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode())); in CreateLiveInRegister()
352 return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()), true); in CreateLiveInRegisterRaw()
359 const SDLoc &SL,
363 const SDLoc &SL,
370 EVT VT, const SDLoc &SL,