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1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
32   /// legalized from a smaller type VT. Need to match pre-legalized type because
39   /// unsigned integer. Truncating to this size and then zero-extending to the
44   /// signed integer. Truncating to this size and then sign-extending to the
141   /// Return 64-bit value Op as two 32-bit integers.
149   /// would otherwise be a 1-vector.
285   // (https://github.com/llvm/llvm-project/commit/db77e57ea86d941a4262ef60261692f4cb6893e6)
288   // MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges;
289   // MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off for
413   // Masked control flow nodes.
430   // Return with values from a non-entry function.
455   // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
482   // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
501   BFE_U32,  // Extract range of bits with zero extension to 32-bits.
502   BFE_I32,  // Extract range of bits with sign extension to 32-bits.
504   BFM,      // Insert a range of bits into a 32-bit word.
505   FFBH_U32, // ctlz with -1 if input is zero.
507   FFBL_B32, // cttz with -1 if input is zero.