Lines Matching +full:use +full:- +full:case
1 //=== lib/CodeGen/GlobalISel/AMDGPUCombinerHelper.cpp ---------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
23 case AMDGPU::G_FADD: in fnegFoldsIntoMI()
24 case AMDGPU::G_FSUB: in fnegFoldsIntoMI()
25 case AMDGPU::G_FMUL: in fnegFoldsIntoMI()
26 case AMDGPU::G_FMA: in fnegFoldsIntoMI()
27 case AMDGPU::G_FMAD: in fnegFoldsIntoMI()
28 case AMDGPU::G_FMINNUM: in fnegFoldsIntoMI()
29 case AMDGPU::G_FMAXNUM: in fnegFoldsIntoMI()
30 case AMDGPU::G_FMINNUM_IEEE: in fnegFoldsIntoMI()
31 case AMDGPU::G_FMAXNUM_IEEE: in fnegFoldsIntoMI()
32 case AMDGPU::G_FMINIMUM: in fnegFoldsIntoMI()
33 case AMDGPU::G_FMAXIMUM: in fnegFoldsIntoMI()
34 case AMDGPU::G_FSIN: in fnegFoldsIntoMI()
35 case AMDGPU::G_FPEXT: in fnegFoldsIntoMI()
36 case AMDGPU::G_INTRINSIC_TRUNC: in fnegFoldsIntoMI()
37 case AMDGPU::G_FPTRUNC: in fnegFoldsIntoMI()
38 case AMDGPU::G_FRINT: in fnegFoldsIntoMI()
39 case AMDGPU::G_FNEARBYINT: in fnegFoldsIntoMI()
40 case AMDGPU::G_INTRINSIC_ROUND: in fnegFoldsIntoMI()
41 case AMDGPU::G_INTRINSIC_ROUNDEVEN: in fnegFoldsIntoMI()
42 case AMDGPU::G_FCANONICALIZE: in fnegFoldsIntoMI()
43 case AMDGPU::G_AMDGPU_RCP_IFLAG: in fnegFoldsIntoMI()
44 case AMDGPU::G_AMDGPU_FMIN_LEGACY: in fnegFoldsIntoMI()
45 case AMDGPU::G_AMDGPU_FMAX_LEGACY: in fnegFoldsIntoMI()
47 case AMDGPU::G_INTRINSIC: { in fnegFoldsIntoMI()
50 case Intrinsic::amdgcn_rcp: in fnegFoldsIntoMI()
51 case Intrinsic::amdgcn_rcp_legacy: in fnegFoldsIntoMI()
52 case Intrinsic::amdgcn_sin: in fnegFoldsIntoMI()
53 case Intrinsic::amdgcn_fmul_legacy: in fnegFoldsIntoMI()
54 case Intrinsic::amdgcn_fmed3: in fnegFoldsIntoMI()
55 case Intrinsic::amdgcn_fma_legacy: in fnegFoldsIntoMI()
66 /// \p returns true if the operation will definitely need to use a 64-bit
67 /// encoding, and thus will use a VOP3 encoding regardless of the source
83 case AMDGPU::COPY: in hasSourceMods()
84 case AMDGPU::G_SELECT: in hasSourceMods()
85 case AMDGPU::G_FDIV: in hasSourceMods()
86 case AMDGPU::G_FREM: in hasSourceMods()
87 case TargetOpcode::INLINEASM: in hasSourceMods()
88 case TargetOpcode::INLINEASM_BR: in hasSourceMods()
89 case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: in hasSourceMods()
90 case AMDGPU::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS: in hasSourceMods()
91 case AMDGPU::G_BITCAST: in hasSourceMods()
92 case AMDGPU::G_ANYEXT: in hasSourceMods()
93 case AMDGPU::G_BUILD_VECTOR: in hasSourceMods()
94 case AMDGPU::G_BUILD_VECTOR_TRUNC: in hasSourceMods()
95 case AMDGPU::G_PHI: in hasSourceMods()
97 case AMDGPU::G_INTRINSIC: in hasSourceMods()
98 case AMDGPU::G_INTRINSIC_CONVERGENT: { in hasSourceMods()
101 case Intrinsic::amdgcn_interp_p1: in hasSourceMods()
102 case Intrinsic::amdgcn_interp_p2: in hasSourceMods()
103 case Intrinsic::amdgcn_interp_mov: in hasSourceMods()
104 case Intrinsic::amdgcn_interp_p1_f16: in hasSourceMods()
105 case Intrinsic::amdgcn_interp_p2_f16: in hasSourceMods()
106 case Intrinsic::amdgcn_div_scale: in hasSourceMods()
119 // Some users (such as 3-operand FMA/MAD) must use a VOP3 encoding, and thus in allUsesHaveSourceMods()
120 // it is truly free to use a source modifier in all cases. If there are in allUsesHaveSourceMods()
126 for (const MachineInstr &Use : MRI.use_nodbg_instructions(Dst)) { in allUsesHaveSourceMods() local
127 if (!hasSourceMods(Use)) in allUsesHaveSourceMods()
130 if (!opMustUseVOP3Encoding(Use, MRI)) { in allUsesHaveSourceMods()
139 const TargetOptions &Options = MI.getMF()->getTarget().Options; in mayIgnoreSignedZero()
159 if (FPValReg->Value.isZero() && !FPValReg->Value.isNegative()) in isConstantCostlierToNegate()
162 const GCNSubtarget &ST = MI.getMF()->getSubtarget<GCNSubtarget>(); in isConstantCostlierToNegate()
163 if (ST.hasInv2PiInlineImm() && isInv2Pi(FPValReg->Value)) in isConstantCostlierToNegate()
171 case AMDGPU::G_FMAXNUM: in inverseMinMax()
173 case AMDGPU::G_FMINNUM: in inverseMinMax()
175 case AMDGPU::G_FMAXNUM_IEEE: in inverseMinMax()
177 case AMDGPU::G_FMINNUM_IEEE: in inverseMinMax()
179 case AMDGPU::G_FMAXIMUM: in inverseMinMax()
181 case AMDGPU::G_FMINIMUM: in inverseMinMax()
183 case AMDGPU::G_AMDGPU_FMAX_LEGACY: in inverseMinMax()
185 case AMDGPU::G_AMDGPU_FMIN_LEGACY: in inverseMinMax()
211 switch (MatchInfo->getOpcode()) { in matchFoldableFneg()
212 case AMDGPU::G_FMINNUM: in matchFoldableFneg()
213 case AMDGPU::G_FMAXNUM: in matchFoldableFneg()
214 case AMDGPU::G_FMINNUM_IEEE: in matchFoldableFneg()
215 case AMDGPU::G_FMAXNUM_IEEE: in matchFoldableFneg()
216 case AMDGPU::G_FMINIMUM: in matchFoldableFneg()
217 case AMDGPU::G_FMAXIMUM: in matchFoldableFneg()
218 case AMDGPU::G_AMDGPU_FMIN_LEGACY: in matchFoldableFneg()
219 case AMDGPU::G_AMDGPU_FMAX_LEGACY: in matchFoldableFneg()
222 MatchInfo->getOperand(2).getReg(), MRI); in matchFoldableFneg()
223 case AMDGPU::G_FADD: in matchFoldableFneg()
224 case AMDGPU::G_FSUB: in matchFoldableFneg()
225 case AMDGPU::G_FMA: in matchFoldableFneg()
226 case AMDGPU::G_FMAD: in matchFoldableFneg()
228 case AMDGPU::G_FMUL: in matchFoldableFneg()
229 case AMDGPU::G_FPEXT: in matchFoldableFneg()
230 case AMDGPU::G_INTRINSIC_TRUNC: in matchFoldableFneg()
231 case AMDGPU::G_FPTRUNC: in matchFoldableFneg()
232 case AMDGPU::G_FRINT: in matchFoldableFneg()
233 case AMDGPU::G_FNEARBYINT: in matchFoldableFneg()
234 case AMDGPU::G_INTRINSIC_ROUND: in matchFoldableFneg()
235 case AMDGPU::G_INTRINSIC_ROUNDEVEN: in matchFoldableFneg()
236 case AMDGPU::G_FSIN: in matchFoldableFneg()
237 case AMDGPU::G_FCANONICALIZE: in matchFoldableFneg()
238 case AMDGPU::G_AMDGPU_RCP_IFLAG: in matchFoldableFneg()
240 case AMDGPU::G_INTRINSIC: in matchFoldableFneg()
241 case AMDGPU::G_INTRINSIC_CONVERGENT: { in matchFoldableFneg()
242 Intrinsic::ID IntrinsicID = cast<GIntrinsic>(MatchInfo)->getIntrinsicID(); in matchFoldableFneg()
244 case Intrinsic::amdgcn_rcp: in matchFoldableFneg()
245 case Intrinsic::amdgcn_rcp_legacy: in matchFoldableFneg()
246 case Intrinsic::amdgcn_sin: in matchFoldableFneg()
247 case Intrinsic::amdgcn_fmul_legacy: in matchFoldableFneg()
248 case Intrinsic::amdgcn_fmed3: in matchFoldableFneg()
250 case Intrinsic::amdgcn_fma_legacy: in matchFoldableFneg()
269 // (if %A has one use, specifically fneg above) in applyFoldableFneg()
302 switch (MatchInfo->getOpcode()) { in applyFoldableFneg()
303 case AMDGPU::G_FADD: in applyFoldableFneg()
304 case AMDGPU::G_FSUB: in applyFoldableFneg()
305 NegateOperand(MatchInfo->getOperand(1)); in applyFoldableFneg()
306 NegateOperand(MatchInfo->getOperand(2)); in applyFoldableFneg()
308 case AMDGPU::G_FMUL: in applyFoldableFneg()
309 NegateEitherOperand(MatchInfo->getOperand(1), MatchInfo->getOperand(2)); in applyFoldableFneg()
311 case AMDGPU::G_FMINNUM: in applyFoldableFneg()
312 case AMDGPU::G_FMAXNUM: in applyFoldableFneg()
313 case AMDGPU::G_FMINNUM_IEEE: in applyFoldableFneg()
314 case AMDGPU::G_FMAXNUM_IEEE: in applyFoldableFneg()
315 case AMDGPU::G_FMINIMUM: in applyFoldableFneg()
316 case AMDGPU::G_FMAXIMUM: in applyFoldableFneg()
317 case AMDGPU::G_AMDGPU_FMIN_LEGACY: in applyFoldableFneg()
318 case AMDGPU::G_AMDGPU_FMAX_LEGACY: { in applyFoldableFneg()
319 NegateOperand(MatchInfo->getOperand(1)); in applyFoldableFneg()
320 NegateOperand(MatchInfo->getOperand(2)); in applyFoldableFneg()
321 unsigned Opposite = inverseMinMax(MatchInfo->getOpcode()); in applyFoldableFneg()
325 case AMDGPU::G_FMA: in applyFoldableFneg()
326 case AMDGPU::G_FMAD: in applyFoldableFneg()
327 NegateEitherOperand(MatchInfo->getOperand(1), MatchInfo->getOperand(2)); in applyFoldableFneg()
328 NegateOperand(MatchInfo->getOperand(3)); in applyFoldableFneg()
330 case AMDGPU::G_FPEXT: in applyFoldableFneg()
331 case AMDGPU::G_INTRINSIC_TRUNC: in applyFoldableFneg()
332 case AMDGPU::G_FRINT: in applyFoldableFneg()
333 case AMDGPU::G_FNEARBYINT: in applyFoldableFneg()
334 case AMDGPU::G_INTRINSIC_ROUND: in applyFoldableFneg()
335 case AMDGPU::G_INTRINSIC_ROUNDEVEN: in applyFoldableFneg()
336 case AMDGPU::G_FSIN: in applyFoldableFneg()
337 case AMDGPU::G_FCANONICALIZE: in applyFoldableFneg()
338 case AMDGPU::G_AMDGPU_RCP_IFLAG: in applyFoldableFneg()
339 case AMDGPU::G_FPTRUNC: in applyFoldableFneg()
340 NegateOperand(MatchInfo->getOperand(1)); in applyFoldableFneg()
342 case AMDGPU::G_INTRINSIC: in applyFoldableFneg()
343 case AMDGPU::G_INTRINSIC_CONVERGENT: { in applyFoldableFneg()
344 Intrinsic::ID IntrinsicID = cast<GIntrinsic>(MatchInfo)->getIntrinsicID(); in applyFoldableFneg()
346 case Intrinsic::amdgcn_rcp: in applyFoldableFneg()
347 case Intrinsic::amdgcn_rcp_legacy: in applyFoldableFneg()
348 case Intrinsic::amdgcn_sin: in applyFoldableFneg()
349 NegateOperand(MatchInfo->getOperand(2)); in applyFoldableFneg()
351 case Intrinsic::amdgcn_fmul_legacy: in applyFoldableFneg()
352 NegateEitherOperand(MatchInfo->getOperand(2), MatchInfo->getOperand(3)); in applyFoldableFneg()
354 case Intrinsic::amdgcn_fmed3: in applyFoldableFneg()
355 NegateOperand(MatchInfo->getOperand(2)); in applyFoldableFneg()
356 NegateOperand(MatchInfo->getOperand(3)); in applyFoldableFneg()
357 NegateOperand(MatchInfo->getOperand(4)); in applyFoldableFneg()
359 case Intrinsic::amdgcn_fma_legacy: in applyFoldableFneg()
360 NegateEitherOperand(MatchInfo->getOperand(2), MatchInfo->getOperand(3)); in applyFoldableFneg()
361 NegateOperand(MatchInfo->getOperand(4)); in applyFoldableFneg()
373 Register MatchInfoDst = MatchInfo->getOperand(0).getReg(); in applyFoldableFneg()
376 // MatchInfo now has negated value so use that instead of old Dst. in applyFoldableFneg()
384 replaceRegOpWith(MRI, MatchInfo->getOperand(0), NegatedMatchInfo); in applyFoldableFneg()
386 // MatchInfo now has negated value so use that instead of old Dst. in applyFoldableFneg()
390 auto NextInst = ++MatchInfo->getIterator(); in applyFoldableFneg()
403 if (Def->getOpcode() == TargetOpcode::G_FPEXT) { in isFPExtFromF16OrConst()
404 Register SrcReg = Def->getOperand(1).getReg(); in isFPExtFromF16OrConst()
408 if (Def->getOpcode() == TargetOpcode::G_FCONSTANT) { in isFPExtFromF16OrConst()
409 APFloat Val = Def->getOperand(1).getFPImm()->getValueAPF(); in isFPExtFromF16OrConst()