149   Type *getI32Ty(IRBuilder<> &B, const Type *T) const;
249   Value* expandDivRem24(IRBuilder<> &Builder, BinaryOperator &I,
253   Value *expandDivRem24Impl(IRBuilder<> &Builder, BinaryOperator &I,
258   Value* expandDivRem32(IRBuilder<> &Builder, BinaryOperator &I,
261   Value *shrinkDivRem64(IRBuilder<> &Builder, BinaryOperator &I,
276   Value *applyFractPat(IRBuilder<> &Builder, Value *FractArg);
281   Value *optimizeWithRsq(IRBuilder<> &Builder, Value *Num, Value *Den,
285   Value *optimizeWithRcp(IRBuilder<> &Builder, Value *Num, Value *Den,
287   Value *optimizeWithFDivFast(IRBuilder<> &Builder, Value *Num, Value *Den,
290   Value *visitFDivElement(IRBuilder<> &Builder, Value *Num, Value *Den,
295   std::pair<Value *, Value *> getFrexpResults(IRBuilder<> &Builder,
298   Value *emitRcpIEEE1ULP(IRBuilder<> &Builder, Value *Src,
300   Value *emitFrexpDiv(IRBuilder<> &Builder, Value *LHS, Value *RHS,
302   Value *emitSqrtIEEE2ULP(IRBuilder<> &Builder, Value *Src,
385 Type *AMDGPUCodeGenPrepareImpl::getI32Ty(IRBuilder<> &B, const Type *T) const {  in getI32Ty()
475   IRBuilder<> Builder(&I);  in promoteUniformOpToI32()
516   IRBuilder<> Builder(&I);  in promoteUniformOpToI32()
543   IRBuilder<> Builder(&I);  in promoteUniformOpToI32()
575   IRBuilder<> Builder(&I);  in promoteUniformBitreverseToI32()
602 static void extractValues(IRBuilder<> &Builder,  in extractValues()
614 static Value *insertValues(IRBuilder<> &Builder,  in insertValues()
644   IRBuilder<> Builder(&I);  in replaceMulWithMul24()
752   IRBuilder<> Builder(&BO);  in foldBinOpIntoSelect()
769 AMDGPUCodeGenPrepareImpl::getFrexpResults(IRBuilder<> &Builder,  in getFrexpResults()
789 Value *AMDGPUCodeGenPrepareImpl::emitRcpIEEE1ULP(IRBuilder<> &Builder,  in emitRcpIEEE1ULP()
813 Value *AMDGPUCodeGenPrepareImpl::emitFrexpDiv(IRBuilder<> &Builder, Value *LHS,  in emitFrexpDiv()
840 Value *AMDGPUCodeGenPrepareImpl::emitSqrtIEEE2ULP(IRBuilder<> &Builder,  in emitSqrtIEEE2ULP()
863 static Value *emitRsqIEEE1ULP(IRBuilder<> &Builder, Value *Src,  in emitRsqIEEE1ULP()
903     IRBuilder<> &Builder, Value *Num, Value *Den, const FastMathFlags DivFMF,  in optimizeWithRsq()
922     IRBuilder<>::FastMathFlagGuard Guard(Builder);  in optimizeWithRsq()
945 AMDGPUCodeGenPrepareImpl::optimizeWithRcp(IRBuilder<> &Builder, Value *Num,  in optimizeWithRcp()
1009     IRBuilder<> &Builder, Value *Num, Value *Den, float ReqdAccuracy) const {  in optimizeWithFDivFast()
1034     IRBuilder<> &Builder, Value *Num, Value *Den, FastMathFlags DivFMF,  in visitFDivElement()
1121   IRBuilder<> Builder(FDiv.getParent(), std::next(FDiv.getIterator()));  in visitFDiv()
1172 static std::pair<Value*, Value*> getMul64(IRBuilder<> &Builder,  in getMul64()
1186 static Value* getMulHu(IRBuilder<> &Builder, Value *LHS, Value *RHS) {  in getMulHu()
1214 Value *AMDGPUCodeGenPrepareImpl::expandDivRem24(IRBuilder<> &Builder,  in expandDivRem24()
1228     IRBuilder<> &Builder, BinaryOperator &I, Value *Num, Value *Den,  in expandDivRem24Impl()
1362 static Value *getSign32(Value *V, IRBuilder<> &Builder, const DataLayout *DL) {  in getSign32()
1372 Value *AMDGPUCodeGenPrepareImpl::expandDivRem32(IRBuilder<> &Builder,  in expandDivRem32()
1497 Value *AMDGPUCodeGenPrepareImpl::shrinkDivRem64(IRBuilder<> &Builder,  in shrinkDivRem64()
1569     IRBuilder<> Builder(&I);  in visitBinaryOperator()
1638     IRBuilder<> Builder(&I);  in visitLoadInst()
1708   IRBuilder<> Builder(&I);  in visitSelectInst()
1918     IRBuilder<> B(BB->getTerminator());  in getSlicedVal()
1986   IRBuilder<> B(I.getParent());  in visitPHINode()
2089   IRBuilder<> B(&I);  in visitAddrSpaceCastInst()
2159 Value *AMDGPUCodeGenPrepareImpl::applyFractPat(IRBuilder<> &Builder,  in applyFractPat()
2186   IRBuilder<> Builder(&I);  in visitMinNum()
2244   IRBuilder<> Builder(&Sqrt);  in visitSqrt()