Lines Matching refs:S32
75 LLT S32 = LLT::scalar(32); in assignValueToReg() local
76 if (Ty != S32) { in assignValueToReg()
81 ExtReg = MIRBuilder.buildPtrToInt(S32, ExtReg).getReg(0); in assignValueToReg()
83 ExtReg = MIRBuilder.buildBitcast(S32, ExtReg).getReg(0); in assignValueToReg()
199 const LLT S32 = LLT::scalar(32); in getStackAddress() local
226 auto OffsetReg = MIRBuilder.buildConstant(S32, Offset); in getStackAddress()
877 const LLT S32 = LLT::scalar(32); in passSpecialInputs() local
889 InputReg = MRI.createGenericVirtualRegister(S32); in passSpecialInputs()
893 InputReg = MIRBuilder.buildConstant(S32, 0).getReg(0); in passSpecialInputs()
899 Register Y = MRI.createGenericVirtualRegister(S32); in passSpecialInputs()
903 Y = MIRBuilder.buildShl(S32, Y, MIRBuilder.buildConstant(S32, 10)).getReg(0); in passSpecialInputs()
904 InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Y).getReg(0) : Y; in passSpecialInputs()
909 Register Z = MRI.createGenericVirtualRegister(S32); in passSpecialInputs()
913 Z = MIRBuilder.buildShl(S32, Z, MIRBuilder.buildConstant(S32, 20)).getReg(0); in passSpecialInputs()
914 InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Z).getReg(0) : Z; in passSpecialInputs()
919 InputReg = MRI.createGenericVirtualRegister(S32); in passSpecialInputs()
933 &AMDGPU::VGPR_32RegClass, S32); in passSpecialInputs()