Lines Matching refs:Regs
250 ? extendRegister(Arg.Regs[ValRegIndex], VA) in assignValueToAddress()
251 : Arg.Regs[ValRegIndex]; in assignValueToAddress()
324 assert(RetInfo.Regs.size() == 1 && "expect only simple return values"); in lowerReturnVal()
327 assert(RetInfo.Regs.size() == 1 && "expect only simple return values"); in lowerReturnVal()
340 if (Reg != RetInfo.Regs[0]) { in lowerReturnVal()
341 RetInfo.Regs[0] = Reg; in lowerReturnVal()
440 assert(SplitArg.Regs.size() == 1); in lowerParameter()
442 B.buildLoad(SplitArg.Regs[0], PtrReg, *MMO); in lowerParameter()
1247 assert(FallbackExecArg.Regs.size() == 1 && in lowerTailCall()
1273 MIB.addReg(Arg.Regs[0]); in lowerTailCall()
1282 assert(ExecArg.Regs.size() == 1 && "Too many regs for EXEC"); in lowerTailCall()
1422 assert(Callee.Regs.size() == 1 && "Too many regs for the callee"); in lowerChainCall()
1423 Info.Callee = MachineOperand::CreateReg(Callee.Regs[0], false); in lowerChainCall()
1589 insertSRetLoads(MIRBuilder, Info.OrigRet.Ty, Info.OrigRet.Regs, in lowerCall()