46                              MachineInstrBuilder MIB)  in AMDGPUOutgoingValueHandler()
47       : OutgoingValueHandler(B, MRI), MIB(MIB) {}  in AMDGPUOutgoingValueHandler()
49   MachineInstrBuilder MIB;  member
93     MIB.addUse(PhysReg, RegState::Implicit);  in assignValueToReg()
167                     MachineInstrBuilder MIB)  in CallReturnHandler()
168       : AMDGPUIncomingArgHandler(MIRBuilder, MRI), MIB(MIB) {}  in CallReturnHandler()
171     MIB.addDef(PhysReg, RegState::Implicit);  in markPhysRegUsed()
174   MachineInstrBuilder MIB;  member
188                            MachineRegisterInfo &MRI, MachineInstrBuilder MIB,  in AMDGPUOutgoingArgHandler()
190       : AMDGPUOutgoingValueHandler(MIRBuilder, MRI, MIB), FPDiff(FPDiff),  in AMDGPUOutgoingArgHandler()
1258   auto MIB = MIRBuilder.buildInstrNoInsert(Opc);  in lowerTailCall()  local
1259   if (!addCallTargetOperands(MIB, MIRBuilder, Info, IsDynamicVGPRChainCall))  in lowerTailCall()
1264   MIB.addImm(0);  in lowerTailCall()
1271         MIB.addImm(CI->getSExtValue());  in lowerTailCall()
1273         MIB.addReg(Arg.Regs[0]);  in lowerTailCall()
1274         unsigned Idx = MIB->getNumOperands() - 1;  in lowerTailCall()
1275         MIB->getOperand(Idx).setReg(constrainOperandRegClass(  in lowerTailCall()
1276             MF, *TRI, MRI, *TII, *ST.getRegBankInfo(), *MIB, MIB->getDesc(),  in lowerTailCall()
1277             MIB->getOperand(Idx), Idx));  in lowerTailCall()
1297   MIB.addRegMask(Mask);  in lowerTailCall()
1362   AMDGPUOutgoingArgHandler Handler(MIRBuilder, MRI, MIB, true, FPDiff);  in lowerTailCall()
1367     MIB.addUse(Info.ConvergenceCtrlToken, RegState::Implicit);  in lowerTailCall()
1369   handleImplicitCallArguments(MIRBuilder, MIB, ST, *FuncInfo, CalleeCC,  in lowerTailCall()
1375     MIB->getOperand(1).setImm(FPDiff);  in lowerTailCall()
1385   MIRBuilder.insertInstr(MIB);  in lowerTailCall()
1393   if (MIB->getOperand(0).isReg()) {  in lowerTailCall()
1394     MIB->getOperand(0).setReg(  in lowerTailCall()
1396                                  *MIB, MIB->getDesc(), MIB->getOperand(0), 0));  in lowerTailCall()
1506   auto MIB = MIRBuilder.buildInstrNoInsert(Opc);  in lowerCall()  local
1507   MIB.addDef(TRI->getReturnAddressReg(MF));  in lowerCall()
1510     MIB.setMIFlag(MachineInstr::NoConvergent);  in lowerCall()
1512   if (!addCallTargetOperands(MIB, MIRBuilder, Info))  in lowerCall()
1517   MIB.addRegMask(Mask);  in lowerCall()
1538   AMDGPUOutgoingArgHandler Handler(MIRBuilder, MRI, MIB, false);  in lowerCall()
1545     MIB.addUse(Info.ConvergenceCtrlToken, RegState::Implicit);  in lowerCall()
1547   handleImplicitCallArguments(MIRBuilder, MIB, ST, *MFI, Info.CallConv,  in lowerCall()
1559   if (MIB->getOperand(1).isReg()) {  in lowerCall()
1560     MIB->getOperand(1).setReg(constrainOperandRegClass(  in lowerCall()
1562         *ST.getRegBankInfo(), *MIB, MIB->getDesc(), MIB->getOperand(1),  in lowerCall()
1567   MIRBuilder.insertInstr(MIB);  in lowerCall()
1576     CallReturnHandler Handler(MIRBuilder, MRI, MIB);  in lowerCall()