Lines Matching refs:CallConv
284 CallingConv::ID CallConv, in canLowerReturn() argument
288 if (AMDGPU::isEntryFunctionCC(CallConv)) in canLowerReturn()
293 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, in canLowerReturn()
296 return checkReturn(CCInfo, Outs, TLI.CCAssignFnForReturn(CallConv, IsVarArg)); in canLowerReturn()
1000 CallingConv::ID CalleeCC = Info.CallConv; in doCallerAndCalleePassArgsTheSameWay()
1046 CallingConv::ID CalleeCC = Info.CallConv; in areCalleeOutgoingArgsTailCallable()
1109 CallingConv::ID CalleeCC = Info.CallConv; in isEligibleForTailCallOptimization()
1194 CallingConv::ID CalleeCC = Info.CallConv; in lowerTailCall()
1215 if (AMDGPU::isChainCC(Info.CallConv)) { in lowerTailCall()
1280 CCState CCInfo(Info.CallConv, Info.IsVarArg, MF, ArgLocs, F.getContext()); in lowerTailCall()
1287 if (Info.CallConv != CallingConv::AMDGPU_Gfx && in lowerTailCall()
1288 !AMDGPU::isChainCC(Info.CallConv)) { in lowerTailCall()
1363 Info.CallConv = F->getCallingConv(); in lowerChainCall()
1367 Info.CallConv = CallingConv::AMDGPU_CS_Chain; // amdgpu_cs_chain_preserve in lowerChainCall()
1382 splitToValueTypes(SGPRArgs, OutArgs, DL, Info.CallConv); in lowerChainCall()
1383 splitToValueTypes(VGPRArgs, OutArgs, DL, Info.CallConv); in lowerChainCall()
1414 splitToValueTypes(OrigArg, OutArgs, DL, Info.CallConv); in lowerCall()
1418 splitToValueTypes(Info.OrigRet, InArgs, DL, Info.CallConv); in lowerCall()
1438 getAssignFnsForCC(Info.CallConv, TLI); in lowerCall()
1447 Info.CallConv); in lowerCall()
1459 const uint32_t *Mask = TRI->getCallPreservedMask(MF, Info.CallConv); in lowerCall()
1463 CCState CCInfo(Info.CallConv, Info.IsVarArg, MF, ArgLocs, F.getContext()); in lowerCall()
1470 if (Info.CallConv != CallingConv::AMDGPU_Gfx) { in lowerCall()
1492 handleImplicitCallArguments(MIRBuilder, MIB, ST, *MFI, Info.CallConv, in lowerCall()
1518 CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv, in lowerCall()
1523 Info.CallConv, Info.IsVarArg)) in lowerCall()