Lines Matching refs:ArgInfo
253 void assignValueToAddress(const CallLowering::ArgInfo &Arg, in assignValueToAddress()
321 SmallVector<ArgInfo, 8> SplitRetInfos; in lowerReturnVal()
326 ArgInfo RetInfo(Reg, VT.getTypeForEVT(Ctx), 0); in lowerReturnVal()
414 void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B, ArgInfo &OrigArg, in lowerParameter()
424 SmallVector<ArgInfo, 32> SplitArgs; in lowerParameter()
429 for (ArgInfo &SplitArg : SplitArgs) { in lowerParameter()
567 ArgInfo OrigArg(VRegs[i], Arg, i); in lowerFormalArgumentsKernel()
620 SmallVector<ArgInfo, 32> SplitArgs; in lowerFormalArguments()
661 ArgInfo OrigArg(VRegs[Idx], Arg, Idx); in lowerFormalArguments()
998 SmallVectorImpl<ArgInfo> &InArgs) const { in doCallerAndCalleePassArgsTheSameWay()
1040 SmallVectorImpl<ArgInfo> &OutArgs) const { in areCalleeOutgoingArgsTailCallable()
1097 SmallVectorImpl<ArgInfo> &InArgs, SmallVectorImpl<ArgInfo> &OutArgs) const { in isEligibleForTailCallOptimization()
1182 SmallVectorImpl<ArgInfo> &OutArgs) const { in lowerTailCall()
1216 ArgInfo ExecArg = Info.OrigArgs[1]; in lowerTailCall()
1345 ArgInfo Callee = Info.OrigArgs[0]; in lowerChainCall()
1346 ArgInfo SGPRArgs = Info.OrigArgs[2]; in lowerChainCall()
1347 ArgInfo VGPRArgs = Info.OrigArgs[3]; in lowerChainCall()
1348 ArgInfo Flags = Info.OrigArgs[4]; in lowerChainCall()
1381 SmallVector<ArgInfo, 8> OutArgs; in lowerChainCall()
1412 SmallVector<ArgInfo, 8> OutArgs; in lowerCall()
1416 SmallVector<ArgInfo, 8> InArgs; in lowerCall()