Lines Matching refs:Zm
1423 : I<(outs zprty:$Zd), (ins VecList:$Zn, zprty:$Zm),
1424 asm, "\t$Zd, $Zn, $Zm",
1428 bits<5> Zm;
1433 let Inst{20-16} = Zm;
1449 def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
1450 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 0>;
1451 def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
1452 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, ZPR16:$Zn, ZPR16:$Zm), 0>;
1453 def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
1454 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, ZPR32:$Zn, ZPR32:$Zm), 0>;
1455 def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
1456 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zm), 0>;
1518 : I<(outs zprty:$Zd), (ins zprty:$_Zd, zprty:$Zn, zprty:$Zm),
1519 asm, "\t$Zd, $Zn, $Zm",
1523 bits<5> Zm;
1528 let Inst{20-16} = Zm;
1739 : I<(outs ZPR8:$Zdn), (ins ZPR8:$_Zdn, ZPR8:$Zm, imm0_255:$imm8),
1740 asm, "\t$Zdn, $_Zdn, $Zm, $imm8",
1743 bits<5> Zm;
1749 let Inst{9-5} = Zm;
1787 : I<(outs zprty:$Zd), (ins PPRAny:$Pg, zprty:$Zn, zprty:$Zm),
1788 asm, "\t$Zd, $Pg, $Zn, $Zm",
1793 bits<5> Zm;
1798 let Inst{20-16} = Zm;
2016 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
2017 asm, "\t$Zd, $Zn, $Zm",
2020 bits<5> Zm;
2025 let Inst{20-16} = Zm;
2094 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
2095 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
2100 bits<5> Zm;
2107 let Inst{9-5} = Zm;
2179 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, timm32_0_7:$imm3),
2180 asm, "\t$Zdn, $_Zdn, $Zm, $imm3",
2184 bits<5> Zm;
2191 let Inst{9-5} = Zm;
2206 def : Pat<(nxv8f16 (op (nxv8f16 ZPR16:$Zn), (nxv8f16 ZPR16:$Zm), (i32 timm32_0_7:$imm))),
2207 (!cast<Instruction>(NAME # _H) ZPR16:$Zn, ZPR16:$Zm, timm32_0_7:$imm)>;
2208 def : Pat<(nxv4f32 (op (nxv4f32 ZPR32:$Zn), (nxv4f32 ZPR32:$Zm), (i32 timm32_0_7:$imm))),
2209 (!cast<Instruction>(NAME # _S) ZPR32:$Zn, ZPR32:$Zm, timm32_0_7:$imm)>;
2210 def : Pat<(nxv2f64 (op (nxv2f64 ZPR64:$Zn), (nxv2f64 ZPR64:$Zm), (i32 timm32_0_7:$imm))),
2211 (!cast<Instruction>(NAME # _D) ZPR64:$Zn, ZPR64:$Zm, timm32_0_7:$imm)>;
2253 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
2254 asm, "\t$Zd, $Zn, $Zm",
2258 bits<5> Zm;
2263 let Inst{20-16} = Zm;
2304 : I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm),
2305 asm, "\t$Zda, $Pg/m, $Zn, $Zm",
2310 bits<5> Zm;
2315 let Inst{20-16} = Zm;
2357 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za),
2358 asm, "\t$Zdn, $Pg/m, $Zm, $Za",
2364 bits<5> Zm;
2372 let Inst{9-5} = Zm;
2403 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty1:$Zn, zprty2:$Zm, itype:$iop),
2404 asm, "\t$Zda, $Zn, $Zm$iop", "", []>, Sched<[]> {
2425 bits<3> Zm;
2429 let Inst{18-16} = Zm;
2438 bits<3> Zm;
2442 let Inst{18-16} = Zm;
2445 bits<3> Zm;
2448 let Inst{18-16} = Zm;
2451 bits<4> Zm;
2454 let Inst{19-16} = Zm;
2472 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty2:$Zm, itype:$iop),
2473 asm, "\t$Zd, $Zn, $Zm$iop", "", []>, Sched<[]> {
2491 bits<3> Zm;
2495 let Inst{18-16} = Zm;
2503 bits<3> Zm;
2507 let Inst{18-16} = Zm;
2510 bits<3> Zm;
2513 let Inst{18-16} = Zm;
2516 bits<4> Zm;
2519 let Inst{19-16} = Zm;
2535 : I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm,
2537 asm, "\t$Zda, $Pg/m, $Zn, $Zm, $imm",
2542 bits<5> Zm;
2547 let Inst{20-16} = Zm;
2581 : I<(outs zprty:$Zda), (ins zprty:$_Zda, zprty:$Zn, zprty2:$Zm, itype:$iop,
2583 asm, "\t$Zda, $Zn, $Zm$iop, $imm",
2605 bits<3> Zm;
2608 let Inst{18-16} = Zm;
2611 bits<4> Zm;
2614 let Inst{19-16} = Zm;
2628 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm,
2630 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm, $imm",
2634 bits<5> Zm;
2643 let Inst{9-5} = Zm;
2721 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
2722 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
2726 bits<5> Zm;
2734 let Inst{9-5} = Zm;
2760 : I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR3b16:$Zm,
2762 asm, "\t$Zda, $Zn, $Zm$iop",
2767 bits<3> Zm;
2773 let Inst{18-16} = Zm;
2801 : I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR16:$Zm),
2802 asm, "\t$Zda, $Zn, $Zm",
2807 bits<5> Zm;
2811 let Inst{20-16} = Zm;
2884 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
2885 asm, "\t$Zd, $Zn, $Zm",
2889 bits<5> Zm;
2894 let Inst{20-16} = Zm;
3091 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
3092 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> {
3095 bits<5> Zm;
3103 let Inst{9-5} = Zm;
3215 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za),
3216 asm, "\t$Zdn, $Pg/m, $Zm, $Za",
3222 bits<5> Zm;
3226 let Inst{20-16} = Zm;
3258 : I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm),
3259 asm, "\t$Zda, $Pg/m, $Zn, $Zm",
3264 bits<5> Zm;
3269 let Inst{20-16} = Zm;
3320 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm),
3321 asm, "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> {
3324 bits<5> Zm;
3328 let Inst{20-16} = Zm;
3369 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty3:$Zm, itype:$iop),
3370 asm, "\t$Zda, $Zn, $Zm$iop", "", []>, Sched<[]> {
3389 bits<3> Zm;
3393 let Inst{18-16} = Zm;
3396 bits<3> Zm;
3399 let Inst{18-16} = Zm;
3402 bits<4> Zm;
3405 let Inst{19-16} = Zm;
3421 bits<3> Zm;
3424 let Inst{18-16} = Zm;
3429 bits<4> Zm;
3432 let Inst{19-16} = Zm;
3446 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm), asm,
3447 "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> {
3450 bits<5> Zm;
3454 let Inst{20-16} = Zm;
3480 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty3:$Zm, itype:$iop),
3481 asm, "\t$Zda, $Zn, $Zm$iop",
3502 bits<3> Zm;
3504 let Inst{18-16} = Zm;
3508 bits<4> Zm;
3510 let Inst{19-16} = Zm;
3523 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm,
3525 asm, "\t$Zda, $Zn, $Zm, $rot", "", []>, Sched<[]> {
3528 bits<5> Zm;
3533 let Inst{20-16} = Zm;
3580 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty3:$Zm, itype:$iop,
3582 asm, "\t$Zda, $Zn, $Zm$iop, $rot", "", []>, Sched<[]> {
3603 bits<3> Zm;
3605 let Inst{18-16} = Zm;
3609 bits<4> Zm;
3611 let Inst{19-16} = Zm;
3630 bits<3> Zm;
3632 let Inst{18-16} = Zm;
3636 bits<4> Zm;
3638 let Inst{19-16} = Zm;
3655 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
3656 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
3658 bits<5> Zm;
3663 let Inst{20-16} = Zm;
3697 : I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty3:$Zm, itype:$iop),
3698 asm, "\t$Zd, $Zn, $Zm$iop", "", []>, Sched<[]> {
3715 bits<3> Zm;
3719 let Inst{18-16} = Zm;
3722 bits<3> Zm;
3725 let Inst{18-16} = Zm;
3728 bits<4> Zm;
3731 let Inst{19-16} = Zm;
3743 bits<3> Zm;
3746 let Inst{18-16} = Zm;
3751 bits<4> Zm;
3754 let Inst{19-16} = Zm;
3768 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
3769 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> {
3771 bits<5> Zm;
3780 let Inst{9-5} = Zm;
3912 : I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty3:$Zm),
3913 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
3916 bits<5> Zm;
3920 let Inst{20-16} = Zm;
3978 : I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty2:$Zm),
3979 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
3982 bits<5> Zm;
3986 let Inst{20-16} = Zm;
4020 : I<(outs zprty1:$Zd), (ins zprty1:$_Zd, zprty2:$Zn, zprty2:$Zm),
4021 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
4024 bits<5> Zm;
4028 let Inst{20-16} = Zm;
4209 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, complexrotateopodd:$rot),
4210 asm, "\t$Zdn, $_Zdn, $Zm, $rot", "", []>, Sched<[]> {
4212 bits<5> Zm;
4220 let Inst{9-5} = Zm;
4243 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm),
4244 asm, "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> {
4247 bits<5> Zm;
4251 let Inst{20-16} = Zm;
4384 : I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty2:$Zm),
4385 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
4388 bits<5> Zm;
4392 let Inst{20-16} = Zm;
4415 : I<(outs zprty1:$Zd), (ins zprty1:$_Zd, zprty2:$Zn, zprty2:$Zm),
4416 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
4419 bits<5> Zm;
4423 let Inst{20-16} = Zm;
4861 : I<(outs ZPR64:$Zd), (ins ZPR64:$Zn, ZPR64:$Zm),
4862 asm, "\t$Zd, $Zn, $Zm",
4866 bits<5> Zm;
4871 let Inst{20-16} = Zm;
4887 def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
4888 (!cast<Instruction>(NAME) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 1>;
4889 def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
4890 (!cast<Instruction>(NAME) ZPR16:$Zd, ZPR16:$Zn, ZPR16:$Zm), 1>;
4891 def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
4892 (!cast<Instruction>(NAME) ZPR32:$Zd, ZPR32:$Zn, ZPR32:$Zm), 1>;
4896 : I<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, ZPR64:$Zm, ZPR64:$Zk),
4897 asm, "\t$Zdn, $_Zdn, $Zm, $Zk",
4902 bits<5> Zm;
4906 let Inst{20-16} = Zm;
4922 def : InstAlias<asm # "\t$Zdn, $Zdn, $Zm, $Zk",
4923 (!cast<Instruction>(NAME) ZPR8:$Zdn, ZPR8:$Zm, ZPR8:$Zk), 1>;
4924 def : InstAlias<asm # "\t$Zdn, $Zdn, $Zm, $Zk",
4925 (!cast<Instruction>(NAME) ZPR16:$Zdn, ZPR16:$Zm, ZPR16:$Zk), 1>;
4926 def : InstAlias<asm # "\t$Zdn, $Zdn, $Zm, $Zk",
4927 (!cast<Instruction>(NAME) ZPR32:$Zdn, ZPR32:$Zm, ZPR32:$Zk), 1>;
4937 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, immtype:$imm),
4938 asm, "\t$Zdn, $_Zdn, $Zm, $imm",
4942 bits<5> Zm;
4950 let Inst{9-5} = Zm;
5122 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty1:$Zn, zprty2:$Zm),
5123 asm, "\t$Pd, $Pg/z, $Zn, $Zm",
5128 bits<5> Zm;
5133 let Inst{20-16} = Zm;
5502 : I<(outs dstOpType:$Vdn), (ins PPR3bAny:$Pg, dstOpType:$_Vdn, zprty:$Zm),
5503 asm, "\t$Vdn, $Pg, $_Vdn, $Zm",
5509 bits<5> Zm;
5516 let Inst{9-5} = Zm;
5543 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm),
5544 asm, "\t$Pd, $Pg/z, $Zn, $Zm",
5549 bits<5> Zm;
5554 let Inst{20-16} = Zm;
5984 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty2:$Zm),
5985 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
5990 bits<5> Zm;
5998 let Inst{9-5} = Zm;
6068 : I<(outs zprty:$Zd), (ins zprty:$Zn, ZPR64:$Zm),
6069 asm, "\t$Zd, $Zn, $Zm",
6073 bits<5> Zm;
6078 let Inst{20-16} = Zm;
6466 : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
6467 asm, "\t$Zt, $Pg, [$Rn, $Zm]",
6472 bits<5> Zm;
6477 let Inst{20-16} = Zm;
6498 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
6499 … (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
6500 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
6501 … (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
6518 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
6519 … (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
6520 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
6521 … (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
6538 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
6539 … (!cast<Instruction>(NAME # _UXTW) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
6540 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
6541 … (!cast<Instruction>(NAME # _SXTW) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
6558 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
6559 … (!cast<Instruction>(NAME # _UXTW) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
6560 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
6561 … (!cast<Instruction>(NAME # _SXTW) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
6571 : I<(outs), (ins Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
6572 asm, "\t$Zt, $Pg, [$Rn, $Zm]",
6577 bits<5> Zm;
6583 let Inst{20-16} = Zm;
6599 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
6600 … (!cast<Instruction>(NAME # _SCALED) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>;
6611 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
6612 … (!cast<Instruction>(NAME) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>;
6859 : I<(outs rt:$Rdn), (ins PPR3bAny:$Pg, rt:$_Rdn, zprty:$Zm),
6860 asm, "\t$Rdn, $Pg, $_Rdn, $Zm",
6865 bits<5> Zm;
6872 let Inst{9-5} = Zm;
6893 : I<(outs rt:$Vdn), (ins PPR3bAny:$Pg, rt:$_Vdn, zprty:$Zm),
6894 asm, "\t$Vdn, $Pg, $_Vdn, $Zm",
6899 bits<5> Zm;
6906 let Inst{9-5} = Zm;
6928 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
6929 asm, "\t$Zdn, $Pg, $_Zdn, $Zm",
6934 bits<5> Zm;
6941 let Inst{9-5} = Zm;
7037 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
7038 asm, "\t$Zdn, $Pg, $_Zdn, $Zm",
7043 bits<5> Zm;
7048 let Inst{9-5} = Zm;
7615 : I<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
7616 asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
7621 bits<5> Zm;
7627 let Inst{20-16} = Zm;
7650 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
7651 … (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
7652 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
7653 … (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
7670 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
7671 … (!cast<Instruction>(NAME # _UXTW) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
7672 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
7673 … (!cast<Instruction>(NAME # _SXTW) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
7777 : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
7778 asm, "\t$prfop, $Pg, [$Rn, $Zm]",
7783 bits<5> Zm;
7788 let Inst{20-16} = Zm;
7807 …def : Pat<(op_uxtw (nxv4i1 PPR3bAny:$Pg), (i64 GPR64sp:$Rn), (nxv4i32 uxtw_opnd:$Zm), (i32 sve_prf…
7808 …ast<Instruction>(NAME # _UXTW_SCALED) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
7810 …def : Pat<(op_sxtw (nxv4i1 PPR3bAny:$Pg), (i64 GPR64sp:$Rn), (nxv4i32 sxtw_opnd:$Zm), (i32 sve_prf…
7811 …ast<Instruction>(NAME # _SXTW_SCALED) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
7966 : I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
7967 asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
7972 bits<5> Zm;
7978 let Inst{20-16} = Zm;
8001 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
8002 … (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
8003 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
8004 … (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
8021 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
8022 … (!cast<Instruction>(NAME # _UXTW) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
8023 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
8024 … (!cast<Instruction>(NAME # _SXTW) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
8037 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
8038 … (!cast<Instruction>(NAME # _SCALED) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>;
8048 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
8049 … (!cast<Instruction>(NAME) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>;
8098 : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
8099 asm, "\t$prfop, $Pg, [$Rn, $Zm]",
8104 bits<5> Zm;
8109 let Inst{20-16} = Zm;
8128 …def : Pat<(op_uxtw (nxv2i1 PPR3bAny:$Pg), (i64 GPR64sp:$Rn), (nxv2i64 uxtw_opnd:$Zm), (i32 sve_prf…
8129 …ast<Instruction>(NAME # _UXTW_SCALED) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
8131 …def : Pat<(op_sxtw (nxv2i1 PPR3bAny:$Pg), (i64 GPR64sp:$Rn), (nxv2i64 sxtw_opnd:$Zm), (i32 sve_prf…
8132 …ast<Instruction>(NAME # _SXTW_SCALED) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
8140 …def : Pat<(frag (nxv2i1 PPR3bAny:$Pg), (i64 GPR64sp:$Rn), (nxv2i64 zprext:$Zm), (i32 sve_prfop:$pr…
8141 (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm)>;
8183 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprext:$Zm),
8184 asm, "\t$Zd, [$Zn, $Zm]",
8189 bits<5> Zm;
8193 let Inst{20-16} = Zm;
8235 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
8236 asm, "\t$Zd, $Zn, $Zm",
8240 bits<5> Zm;
8245 let Inst{20-16} = Zm;
8523 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm),
8524 asm, "\t$Pd, $Pg/z, $Zn, $Zm",
8529 bits<5> Zm;
8534 let Inst{20-16} = Zm;
8560 : I<(outs ZPR8:$Zd), (ins ZPR8:$Zn, ZPR8:$Zm),
8561 asm, "\t$Zd, $Zn, $Zm",
8563 [(set nxv16i8:$Zd, (op nxv16i8:$Zn, nxv16i8:$Zm))]>, Sched<[]> {
8566 bits<5> Zm;
8568 let Inst{20-16} = Zm;
8581 : I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm),
8582 asm, "\t$Zd, $Pg/z, $Zn, $Zm",
8588 bits<5> Zm;
8592 let Inst{20-16} = Zm;
8614 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
8615 asm, "\t$Zd, $Zn, $Zm",
8620 bits<5> Zm;
8622 let Inst{20-16} = Zm;
8638 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm),
8639 asm, "\t$Zdn, $_Zdn, $Zm",
8643 bits<5> Zm;
8648 let Inst{9-5} = Zm;
8686 : I<(outs dst_ty:$Zda), (ins dst_ty:$_Zda, src_ty:$Zn, src_ty:$Zm),
8687 asm, "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> {
8690 bits<5> Zm;
8694 let Inst{20-16} = Zm;
8714 : I<(outs dst_ty:$Zda), (ins dst_ty:$_Zda, src1_ty:$Zn, src2_ty:$Zm, iop_ty:$iop),
8715 asm, "\t$Zda, $Zn, $Zm$iop", "", []>, Sched<[]> {
8718 bits<3> Zm;
8722 let Inst{18-16} = Zm;
8745 : I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR16:$Zm),
8746 asm, "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> {
8747 bits<5> Zm;
8751 let Inst{20-16} = Zm;
8798 : I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR8:$Zn, ZPR8:$Zm), asm,
8799 "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> {
8802 bits<5> Zm;
8806 let Inst{20-16} = Zm;
8828 : I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR8:$Zn, ZPR8:$Zm), asm,
8829 "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> {
8832 bits<5> Zm;
8834 let Inst{20-16} = Zm;
8856 : I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR8:$Zn, ZPR3b8:$Zm, VectorIndexS32b:$idx),
8857 asm, "\t$Zda, $Zn, $Zm$idx", "", []>, Sched<[]> {
8860 bits<3> Zm;
8864 let Inst{18-16} = Zm;
8887 : I<(outs zprty:$Zda), (ins zprty:$_Zda, zprty:$Zn, zprty:$Zm),
8888 asm, "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> {
8891 bits<5> Zm;
8895 let Inst{20-16} = Zm;
8995 : I<(outs ZPR128:$Zd), (ins ZPR128:$Zn, ZPR128:$Zm),
8996 asm, "\t$Zd, $Zn, $Zm",
9000 bits<5> Zm;
9003 let Inst{20-16} = Zm;
9125 : I<(outs zpr_ty:$Zd), (ins zpr_ty:$_Zd, zpr_ty:$Zn, zpr_ty:$Zm),
9126 asm, "\t$Zd, $Zn, $Zm", "", []>,
9128 bits<5> Zm;
9134 let Inst{20-16} = Zm;
9162 : I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR16:$Zm),
9163 mnemonic, "\t$Zda, $Zn, $Zm",
9167 bits<5> Zm;
9169 let Inst{20-16} = Zm;
9188 : I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR3b16:$Zm, VectorIndexS32b:$i2),
9189 mnemonic, "\t$Zda, $Zn, $Zm$i2",
9193 bits<3> Zm;
9197 let Inst{18-16} = Zm;
9940 : I<(outs ZPR8:$Zdn), (ins ZPR8:$_Zdn, ZPR8:$Zm, timm32_0_15:$imm4),
9941 mnemonic, "\t$Zdn, $_Zdn, $Zm, $imm4",
9944 bits<5> Zm;
9949 let Inst{9-5} = Zm;
10143 : I<(outs zpr_ty:$Zd), (ins src1_ty:$Zn, zpr_ty:$Zm),
10144 mnemonic, "\t$Zd, $Zn, $Zm",
10148 bits<5> Zm;
10152 let Inst{20-16} = Zm;
10244 (ins ZPR16:$_Zda, ZPR8:$Zn, ZPR3b8:$Zm, VectorIndexB:$imm4),
10245 mnemonic, "\t$Zda, $Zn, $Zm$imm4",
10249 bits<3> Zm;
10255 let Inst{18-16} = Zm;
10268 (ins dst_ty:$_Zda, ZPR8:$Zn, ZPR8:$Zm),
10269 mnemonic, "\t$Zda, $Zn, $Zm",
10273 bits<5> Zm;
10277 let Inst{20-16} = Zm;
10291 (ins ZPR32:$_Zda, ZPR8:$Zn, ZPR3b8:$Zm, VectorIndexB:$imm4),
10292 mnemonic, "\t$Zda, $Zn, $Zm$imm4",
10296 bits<3> Zm;
10302 let Inst{18-16} = Zm;
10325 : I<(outs zd_ty:$Zd), (ins zn_ty:$Zn, ZPRAny:$Zm, idx_ty:$idx),
10326 mnemonic, "\t$Zd, $Zn, $Zm$idx",
10330 bits<5> Zm;
10334 let Inst{20-16} = Zm;
10378 : I<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, ZPR64:$Zm, ZPR64:$Za),
10379 asm, "\t$Zdn, $Zm, $Za", "", []>, Sched<[]> {
10381 bits<5> Zm;
10386 let Inst{20-16} = Zm;