Lines Matching refs:Pn
765 : I<(outs), (ins PPRAny:$Pg, PPR8:$Pn),
766 asm, "\t$Pg, $Pn",
768 [(op (nxv16i1 PPRAny:$Pg), (nxv16i1 PPR8:$Pn))]>, Sched<[]> {
770 bits<4> Pn;
778 let Inst{8-5} = Pn;
791 def _ANY : Pseudo<(outs), (ins PPRAny:$Pg, PPR8:$Pn),
792 [(op_any (nxv16i1 PPRAny:$Pg), (nxv16i1 PPR8:$Pn))]>,
793 PseudoInstExpansion<(!cast<Instruction>(NAME) PPRAny:$Pg, PPR8:$Pn)>;
1031 : I<(outs GPR64:$Rd), (ins PPRAny:$Pg, pprty:$Pn),
1032 asm, "\t$Rd, $Pg, $Pn",
1036 bits<4> Pn;
1045 let Inst{8-5} = Pn;
1598 : I<(outs pprty:$Pd), (ins pprty:$Pn),
1599 asm, "\t$Pd, $Pn",
1601 [(set nxv16i1:$Pd, (op nxv16i1:$Pn))]>, Sched<[]> {
1603 bits<4> Pn;
1607 let Inst{8-5} = Pn;
1843 : I<(outs PPRorPNR8:$Pd), (ins PPRorPNRAny:$Pg, PPRorPNR8:$Pn, PPRorPNR8:$Pm),
1844 asm, "\t$Pd, $Pg/z, $Pn, $Pm",
1850 bits<4> Pn;
1858 let Inst{8-5} = Pn;
1864 !strconcat(asm, "\t$Pd, $Pg, $Pn, $Pm"),
1865 !strconcat(asm, "\t$Pd, $Pg/z, $Pn, $Pm"));
6735 : I<(outs pprty:$Pd), (ins pprty:$Pn, pprty:$Pm),
6736 asm, "\t$Pd, $Pn, $Pm",
6738 [(set nxv16i1:$Pd, (op nxv16i1:$Pn, nxv16i1:$Pm))]>, Sched<[]> {
6741 bits<4> Pn;
6749 let Inst{8-5} = Pn;
6772 : I<(outs PPR16:$Pd), (ins PPR8:$Pn),
6773 asm, "\t$Pd, $Pn",
6777 bits<4> Pn;
6781 let Inst{8-5} = Pn;
6829 : I<(outs), (ins PPR8:$Pn),
6830 asm, "\t$Pn",
6832 [(op (nxv16i1 PPR8:$Pn))]>, Sched<[]> {
6833 bits<4> Pn;
6835 let Inst{8-5} = Pn;
8419 : I<(outs PPR8:$Pd), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$Pm),
8420 asm, "\t$Pd, $Pg/z, $Pn, $Pm",
8426 bits<4> Pn;
8435 let Inst{8-5} = Pn;
8455 : I<(outs PPR8:$Pdm), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$_Pdm),
8456 asm, "\t$Pdm, $Pg/z, $Pn, $_Pdm",
8461 bits<4> Pn;
8467 let Inst{8-5} = Pn;
8485 asm, "\t$Pd, $Pg"#suffix#", $Pn",
8490 bits<4> Pn;
8496 let Inst{8-5} = Pn;
8506 def NAME : sve_int_break<opc, asm, "/m", (ins PPR8:$_Pd, PPRAny:$Pg, PPR8:$Pn)>;
8512 def NAME : sve_int_break<opc, asm, "/z", (ins PPRAny:$Pg, PPR8:$Pn)>;
10041 : I<(outs ZPRAny:$Zd), (ins ZPRAny:$_Zd, itype:$index, ppr_ty:$Pn),
10042 mnemonic, "\t$Zd$index, $Pn",
10045 bits<4> Pn;
10051 let Inst{8-5} = Pn;
10075 def : InstAlias<mnemonic # "\t$Zd, $Pn",
10076 (!cast<Instruction>(NAME # _B) ZPRAny:$Zd, 0, PPR8:$Pn), 1>;
10077 def : InstAlias<mnemonic # "\t$Zd, $Pn",
10078 (!cast<Instruction>(NAME # _H) ZPRAny:$Zd, 0, PPR16:$Pn), 0>;
10079 def : InstAlias<mnemonic # "\t$Zd, $Pn",
10080 (!cast<Instruction>(NAME # _S) ZPRAny:$Zd, 0, PPR32:$Pn), 0>;
10081 def : InstAlias<mnemonic # "\t$Zd, $Pn",
10082 (!cast<Instruction>(NAME # _D) ZPRAny:$Zd, 0, PPR64:$Pn), 0>;
10085 def : Pat<(nxv8i16 (MergeOp (nxv8i16 ZPRAny:$Zd), (nxv8i1 PPR16:$Pn), (i32 timm32_1_1:$Idx))),
10086 (!cast<Instruction>(NAME # _H) ZPRAny:$Zd, timm32_1_1:$Idx, PPR16:$Pn)>;
10087 def : Pat<(nxv4i32 (MergeOp (nxv4i32 ZPRAny:$Zd), (nxv4i1 PPR32:$Pn), (i32 timm32_1_3:$Idx))),
10088 (!cast<Instruction>(NAME # _S) ZPRAny:$Zd, timm32_1_3:$Idx, PPR32:$Pn)>;
10089 def : Pat<(nxv2i64 (MergeOp (nxv2i64 ZPRAny:$Zd), (nxv2i1 PPR64:$Pn), (i32 timm32_1_7:$Idx))),
10090 (!cast<Instruction>(NAME # _D) ZPRAny:$Zd, timm32_1_7:$Idx, PPR64:$Pn)>;
10093 def : Pat<(nxv16i8 (ZeroOp (nxv16i1 PPR8:$Pn))),
10094 (!cast<Instruction>(NAME # _B) (IMPLICIT_DEF), 0, PPR8:$Pn)>;
10095 def : Pat<(nxv8i16 (ZeroOp (nxv8i1 PPR16:$Pn))),
10096 (!cast<Instruction>(NAME # _H) (IMPLICIT_DEF), 0, PPR16:$Pn)>;
10097 def : Pat<(nxv4i32 (ZeroOp (nxv4i1 PPR32:$Pn))),
10098 (!cast<Instruction>(NAME # _S) (IMPLICIT_DEF), 0, PPR32:$Pn)>;
10099 def : Pat<(nxv2i64 (ZeroOp (nxv2i1 PPR64:$Pn))),
10100 (!cast<Instruction>(NAME # _D) (IMPLICIT_DEF), 0, PPR64:$Pn)>;