Lines Matching refs:MCInst
23 #include "llvm/MC/MCInst.h"
55 uint64_t getBinaryCodeForInstr(const MCInst &MI,
61 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
69 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
75 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
81 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
87 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
93 uint32_t getPAuthPCRelOpValue(const MCInst &MI, unsigned OpIdx,
99 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
106 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
112 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
118 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
124 uint32_t getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
129 uint32_t getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
135 uint32_t getMoveVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
141 uint32_t getFixedPointScaleOpValue(const MCInst &MI, unsigned OpIdx,
145 uint32_t getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx,
148 uint32_t getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx,
151 uint32_t getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx,
154 uint32_t getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx,
157 uint32_t getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx,
160 uint32_t getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx,
163 uint32_t getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx,
166 uint32_t getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx,
170 uint32_t getImm8OptLsl(const MCInst &MI, unsigned OpIdx,
173 uint32_t getSVEIncDecImm(const MCInst &MI, unsigned OpIdx,
177 unsigned fixMOVZ(const MCInst &MI, unsigned EncodedValue,
180 void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
184 unsigned fixMulHigh(const MCInst &MI, unsigned EncodedValue,
188 fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue,
191 unsigned fixOneOperandFPComparison(const MCInst &MI, unsigned EncodedValue,
195 uint32_t EncodeRegAsMultipleOf(const MCInst &MI, unsigned OpIdx,
198 uint32_t EncodePNR_p8to15(const MCInst &MI, unsigned OpIdx,
202 uint32_t EncodeZPR2StridedRegisterClass(const MCInst &MI, unsigned OpIdx,
205 uint32_t EncodeZPR4StridedRegisterClass(const MCInst &MI, unsigned OpIdx,
209 uint32_t EncodeMatrixTileListRegisterClass(const MCInst &MI, unsigned OpIdx,
213 uint32_t encodeMatrixIndexGPR32(const MCInst &MI, unsigned OpIdx,
223 AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
234 AArch64MCCodeEmitter::getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
255 AArch64MCCodeEmitter::getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
281 AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
318 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
339 AArch64MCCodeEmitter::getPAuthPCRelOpValue(const MCInst &MI, unsigned OpIdx,
362 AArch64MCCodeEmitter::getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
382 AArch64MCCodeEmitter::getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
391 AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
411 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
432 AArch64MCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
460 AArch64MCCodeEmitter::getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
485 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
493 AArch64MCCodeEmitter::getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx,
502 AArch64MCCodeEmitter::getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx,
511 AArch64MCCodeEmitter::getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx,
520 AArch64MCCodeEmitter::getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx,
529 AArch64MCCodeEmitter::getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx,
538 AArch64MCCodeEmitter::getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx,
547 AArch64MCCodeEmitter::getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx,
556 AArch64MCCodeEmitter::getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx,
566 AArch64MCCodeEmitter::EncodeRegAsMultipleOf(const MCInst &MI, unsigned OpIdx,
576 AArch64MCCodeEmitter::EncodePNR_p8to15(const MCInst &MI, unsigned OpIdx,
584 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
594 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
604 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
613 AArch64MCCodeEmitter::encodeMatrixIndexGPR32(const MCInst &MI, unsigned OpIdx,
621 AArch64MCCodeEmitter::getImm8OptLsl(const MCInst &MI, unsigned OpIdx,
639 AArch64MCCodeEmitter::getSVEIncDecImm(const MCInst &MI, unsigned OpIdx,
651 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
661 unsigned AArch64MCCodeEmitter::fixMOVZ(const MCInst &MI, unsigned EncodedValue,
693 void AArch64MCCodeEmitter::encodeInstruction(const MCInst &MI,
722 AArch64MCCodeEmitter::fixMulHigh(const MCInst &MI,
732 AArch64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI,
742 const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const {