Lines Matching refs:ShuffleVectorPseudo
72 struct ShuffleVectorPseudo { struct
76 ShuffleVectorPseudo(unsigned Opc, Register Dst, in ShuffleVectorPseudo() argument
79 ShuffleVectorPseudo() = default;
158 ShuffleVectorPseudo &MatchInfo) { in matchREV()
183 MatchInfo = ShuffleVectorPseudo(Opcode, Dst, {Src}); in matchREV()
194 ShuffleVectorPseudo &MatchInfo) { in matchTRN()
205 MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2}); in matchTRN()
215 ShuffleVectorPseudo &MatchInfo) { in matchUZP()
226 MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2}); in matchUZP()
231 ShuffleVectorPseudo &MatchInfo) { in matchZip()
242 MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2}); in matchZip()
249 ShuffleVectorPseudo &MatchInfo) { in matchDupFromInsertVectorElt()
281 MatchInfo = ShuffleVectorPseudo(AArch64::G_DUP, MI.getOperand(0).getReg(), in matchDupFromInsertVectorElt()
289 ShuffleVectorPseudo &MatchInfo) { in matchDupFromBuildVector()
299 ShuffleVectorPseudo(AArch64::G_DUP, MI.getOperand(0).getReg(), {Reg}); in matchDupFromBuildVector()
304 ShuffleVectorPseudo &MatchInfo) { in matchDup()
350 ShuffleVectorPseudo &MatchInfo) { in matchEXT()
367 MatchInfo = ShuffleVectorPseudo(AArch64::G_EXT, Dst, {V1, V1, Imm}); in matchEXT()
375 MatchInfo = ShuffleVectorPseudo(AArch64::G_EXT, Dst, {V1, V2, Imm}); in matchEXT()
382 ShuffleVectorPseudo &MatchInfo) { in applyShuffleVectorPseudo()
391 void applyEXT(MachineInstr &MI, ShuffleVectorPseudo &MatchInfo) { in applyEXT()