512   bool tryOptimizeConsecStores(SmallVectorImpl<StoreInfo> &Stores,
580     SmallVectorImpl<StoreInfo> &Stores, CSEMIRBuilder &MIB) {  in tryOptimizeConsecStores()  argument
581   if (Stores.size() <= 2)  in tryOptimizeConsecStores()
585   int64_t BaseOffset = Stores[0].Offset;  in tryOptimizeConsecStores()
586   unsigned NumPairsExpected = Stores.size() / 2;  in tryOptimizeConsecStores()
587   unsigned TotalInstsExpected = NumPairsExpected + (Stores.size() % 2);  in tryOptimizeConsecStores()
593   int SavingsExpected = Stores.size() - TotalInstsExpected;  in tryOptimizeConsecStores()
601   Register NewBase = Stores[0].Ptr->getReg(0);  in tryOptimizeConsecStores()
602   for (auto &SInfo : Stores) {  in tryOptimizeConsecStores()
614   LLVM_DEBUG(dbgs() << "Split a series of " << Stores.size()  in tryOptimizeConsecStores()
654   SmallVector<StoreInfo, 8> Stores;  in optimizeConsecutiveMemOpAddressing()  local
701     return New.Offset - Stores[0].Offset <= MaxLegalOffset;  in optimizeConsecutiveMemOpAddressing()
705     Stores.clear();  in optimizeConsecutiveMemOpAddressing()
734           if (Stores.empty()) {  in optimizeConsecutiveMemOpAddressing()
735             Stores.push_back(New);  in optimizeConsecutiveMemOpAddressing()
740           auto &Last = Stores.back();  in optimizeConsecutiveMemOpAddressing()
742             Stores.push_back(New);  in optimizeConsecutiveMemOpAddressing()
747             Changed |= tryOptimizeConsecStores(Stores, MIB);  in optimizeConsecutiveMemOpAddressing()
749             Stores.push_back(New);  in optimizeConsecutiveMemOpAddressing()
756     Changed |= tryOptimizeConsecStores(Stores, MIB);  in optimizeConsecutiveMemOpAddressing()