85   if (DstSize != 16 && DstSize != 32 && DstSize != 64)  in matchExtractVecEltPairwiseAdd()
117   LLT s64 = LLT::scalar(64);  in applyExtractVecEltPairwiseAdd()
156   // 64-bit is 5 cycles, so this is always a win.  in matchAArch64MulConstCombine()
226     auto Shift = B.buildConstant(LLT::scalar(64), ShiftAmt);  in matchAArch64MulConstCombine()
241       B.buildShl(DstReg, Res, B.buildConstant(LLT::scalar(64), TrailingZeroes));  in matchAArch64MulConstCombine()
305 /// Match a 128b store of zero and split it into two 64 bit stores, for
332   LLT NewTy = LLT::scalar(64);  in applySplitStoreZero128()
336                                B.buildConstant(LLT::scalar(64), 8));  in applySplitStoreZero128()
391   if (DstTy != LLT::fixed_vector(2, 64) && DstTy != LLT::fixed_vector(2, 32) &&  in matchCombineMulCMLT()
513                                CSEMIRBuilder &MIB);
516                                           CSEMIRBuilder &MIB);
573   auto MIB = CSEMIRBuilder(MF);  in runOnMachineFunction()  local
574   MIB.setCSEInfo(CSEInfo);  in runOnMachineFunction()
575   Changed |= optimizeConsecutiveMemOpAddressing(MF, MIB);  in runOnMachineFunction()
580     SmallVectorImpl<StoreInfo> &Stores, CSEMIRBuilder &MIB) {  in tryOptimizeConsecStores()  argument
590   auto &TLI = *MIB.getMF().getSubtarget().getTargetLowering();  in tryOptimizeConsecStores()
597   auto &MRI = MIB.getMF().getRegInfo();  in tryOptimizeConsecStores()
604     MIB.setInstrAndDebugLoc(*SInfo.St);  in tryOptimizeConsecStores()
605     auto NewOff = MIB.buildConstant(LLT::scalar(64), SInfo.Offset - BaseOffset);  in tryOptimizeConsecStores()
606     auto NewPtr = MIB.buildPtrAdd(MRI.getType(SInfo.St->getPointerReg()),  in tryOptimizeConsecStores()
608     if (MIB.getObserver())  in tryOptimizeConsecStores()
609       MIB.getObserver()->changingInstr(*SInfo.St);  in tryOptimizeConsecStores()
611     if (MIB.getObserver())  in tryOptimizeConsecStores()
612       MIB.getObserver()->changedInstr(*SInfo.St);  in tryOptimizeConsecStores()
626     MachineFunction &MF, CSEMIRBuilder &MIB) {  in optimizeConsecutiveMemOpAddressing()  argument
688     case 64:  in optimizeConsecutiveMemOpAddressing()
747             Changed |= tryOptimizeConsecStores(Stores, MIB);  in optimizeConsecutiveMemOpAddressing()
756     Changed |= tryOptimizeConsecStores(Stores, MIB);  in optimizeConsecutiveMemOpAddressing()