Lines Matching +full:pre +full:- +full:multiply

1 //==-- AArch64Schedule.td - AArch64 Scheduling Definitions -*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14     static_cast<const AArch64InstrInfo*>(SchedModel->getInstrInfo());
25 def WriteISReg     : SchedWrite; // ALU of Shifted-Reg
26 def WriteIEReg     : SchedWrite; // ALU of Extended-Reg
28 def ReadISReg      : SchedRead;  // ALU of Shifted-Reg
29 def ReadIEReg      : SchedRead;  // ALU of Extended-Reg
33 def WriteID32      : SchedWrite; // 32-bit Divide
34 def WriteID64      : SchedWrite; // 64-bit Divide
35 def ReadID         : SchedRead;  // 32/64-bit Divide
36 def WriteIM32      : SchedWrite; // 32-bit Multiply
37 def WriteIM64      : SchedWrite; // 64-bit Multiply
38 def ReadIM         : SchedRead;  // 32/64-bit Multiply
39 def ReadIMA        : SchedRead;  // 32/64-bit Multiply Accumulate
46 def WriteAdr       : SchedWrite; // Address pre/post increment.
51 def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST.
53 // Serialized two-level address load.
57 // Serialized two-level address lookup.
61 // The second register of a load-pair.
65 // Store-exclusive is a store followed by a dependent load.
72 def WriteF       : SchedWrite; // General floating-point ops.
73 def WriteFCmp    : SchedWrite; // Floating-point compare.
75 def WriteFCopy   : SchedWrite; // Float-int register copy.
76 def WriteFImm    : SchedWrite; // Floating-point immediate.
77 def WriteFMul    : SchedWrite; // Floating-point multiply.
78 def WriteFDiv    : SchedWrite; // Floating-point division.