Lines Matching +full:pre +full:- +full:multiply
1 //=- AArch64SchedThunderX3T110.td - Marvell ThunderX3 T110 ---*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
18 let IssueWidth = 4; // 4 micro-ops dispatched at a time.
19 let MicroOpBufferSize = 70; // 70 entries in micro-op re-order buffer.
22 // Determined via a mix of micro-arch details and experimentation.
75 // Integer divide/mulhi micro-ops only on port I1.
78 // Branch micro-ops on ports I2/I3.
81 // Branch micro-ops on ports I1/I2/I3.
84 // Integer micro-ops on ports I0/I1/I2.
87 // Integer micro-ops on ports I0/I1/I2/I3.
91 // FP micro-ops on ports FP0/FP1/FP2/FP3.
95 // FP micro-ops on ports FP2/FP3.
98 // ASIMD micro-ops on ports FP0/FP1/FP2/FP3.
102 // Store data micro-ops only on port 10.
105 // Load/store micro-ops on ports P4/P5.
325 // Load vector pair, immed offset, Q-form [LDP/LDNP].
335 // Load vector pair, immed offset, S/D-form [LDP/LDNP].
628 //===----------------------------------------------------------------------===//
631 //---
633 //---
660 //---
662 //---
669 //---
672 //---
757 //---
758 // 3.4 Divide and Multiply Instructions
759 //---
761 // Divide, W-form
762 // Latency range of 13-23/13-39.
769 // Divide, X-form
776 // Multiply accumulate, W-form
782 // Multiply accumulate, X-form
804 // Multiply high
807 // Miscellaneous Data-Processing Instructions
811 // Bitifield move - basic
847 //---
850 //---
861 // Load register, immed post-index
863 // Load register, immed pre-index
873 // LDP only breaks into *one* LS micro-op. Thus
896 // Load pair, immed pre-index, normal
897 // Load pair, immed pre-index, signed words
898 // Load pair, immed post-index, normal
899 // Load pair, immed post-index, signed words
1017 //---
1019 //---
1026 //--
1029 //--
1039 // Store register, immed post-index
1042 // Store register, immed pre-index
1056 // Store pair, immed offset, W-form
1057 // Store pair, immed offset, X-form
1063 // Store pair, immed post-index, W-form
1064 // Store pair, immed post-index, X-form
1065 // Store pair, immed pre-index, W-form
1066 // Store pair, immed pre-index, X-form
1197 //---
1199 //---
1254 // FP divide, S-form
1255 // FP square root, S-form
1262 // FP divide, D-form
1263 // FP square root, D-form
1270 // FP multiply
1271 // FP multiply accumulate
1301 //---
1303 //---
1329 //---
1331 //---
1333 // ASIMD absolute diff, D-form
1334 // ASIMD absolute diff, Q-form
1335 // ASIMD absolute diff accum, D-form
1336 // ASIMD absolute diff accum, Q-form
1347 // ASIMD multiply, D-form
1348 // ASIMD multiply, Q-form
1349 // ASIMD multiply accumulate long
1350 // ASIMD multiply accumulate saturating long
1351 // ASIMD multiply long
1355 // ASIMD shift by immed and insert, basic, D-form
1356 // ASIMD shift by immed and insert, basic, Q-form
1358 // ASIMD shift by register, basic, D-form
1359 // ASIMD shift by register, basic, Q-form
1360 // ASIMD shift by register, complex, D-form
1361 // ASIMD shift by register, complex, Q-form
1385 // ASIMD polynomial (8x8) multiply long
1392 // ASIMD absolute diff accum, D-form
1395 // ASIMD absolute diff accum, Q-form
1419 // ASIMD multiply, D-form
1424 // ASIMD multiply, Q-form
1427 // ASIMD multiply accumulate, D-form
1430 // ASIMD multiply accumulate, Q-form
1445 // ASIMD shift by register, basic, Q-form
1448 // ASIMD shift by register, complex, D-form
1452 // ASIMD shift by register, complex, Q-form
1497 //---
1498 // 3.13 ASIMD Floating-point Instructions
1499 //---
1504 // ASIMD FP arith, normal, D-form
1505 // ASIMD FP arith, normal, Q-form
1509 // ASIMD FP arith,pairwise, D-form
1510 // ASIMD FP arith, pairwise, Q-form
1513 // ASIMD FP compare, D-form
1514 // ASIMD FP compare, Q-form
1520 // ASIMD FP round, D-form
1523 // ASIMD FP round, Q-form
1529 // ASIMD FP convert, other, D-form
1530 // ASIMD FP convert, other, Q-form
1535 // ASIMD FP convert, other, D-form
1538 // ASIMD FP convert, other, Q-form
1542 // ASIMD FP divide, D-form, F32
1546 // ASIMD FP divide, Q-form, F32
1550 // ASIMD FP divide, Q-form, F64
1554 // ASIMD FP max/min, normal, D-form
1555 // ASIMD FP max/min, normal, Q-form
1559 // ASIMD FP max/min, pairwise, D-form
1560 // ASIMD FP max/min, pairwise, Q-form
1568 // ASIMD FP multiply, D-form, FZ
1569 // ASIMD FP multiply, D-form, no FZ
1570 // ASIMD FP multiply, Q-form, FZ
1571 // ASIMD FP multiply, Q-form, no FZ
1579 // ASIMD FP multiply accumulate, Dform, FZ
1580 // ASIMD FP multiply accumulate, Dform, no FZ
1581 // ASIMD FP multiply accumulate, Qform, FZ
1582 // ASIMD FP multiply accumulate, Qform, no FZ
1593 //--
1595 //--
1600 // ASIMD bitwise insert, D-form
1601 // ASIMD bitwise insert, Q-form
1605 // ASIMD count, D-form
1606 // ASIMD count, Q-form
1645 // ASIMD reciprocal estimate, D-form
1646 // ASIMD reciprocal estimate, Q-form
1651 // ASIMD reciprocal step, D-form, FZ
1652 // ASIMD reciprocal step, D-form, no FZ
1653 // ASIMD reciprocal step, Q-form, FZ
1654 // ASIMD reciprocal step, Q-form, no FZ
1662 // ASIMD table lookup, D-form
1663 // ASIMD table lookup, Q-form
1689 //--
1691 //--
1693 // ASIMD load, 1 element, multiple, 1 reg, D-form
1694 // ASIMD load, 1 element, multiple, 1 reg, Q-form
1700 // ASIMD load, 1 element, multiple, 2 reg, D-form
1701 // ASIMD load, 1 element, multiple, 2 reg, Q-form
1707 // ASIMD load, 1 element, multiple, 3 reg, D-form
1708 // ASIMD load, 1 element, multiple, 3 reg, Q-form
1714 // ASIMD load, 1 element, multiple, 4 reg, D-form
1715 // ASIMD load, 1 element, multiple, 4 reg, Q-form
1728 // ASIMD load, 1 element, all lanes, D-form, B/H/S
1729 // ASIMD load, 1 element, all lanes, D-form, D
1730 // ASIMD load, 1 element, all lanes, Q-form
1736 // ASIMD load, 2 element, multiple, D-form, B/H/S
1737 // ASIMD load, 2 element, multiple, Q-form, D
1751 // ASIMD load, 2 element, all lanes, D-form, B/H/S
1752 // ASIMD load, 2 element, all lanes, D-form, D
1753 // ASIMD load, 2 element, all lanes, Q-form
1759 // ASIMD load, 3 element, multiple, D-form, B/H/S
1760 // ASIMD load, 3 element, multiple, Q-form, B/H/S
1761 // ASIMD load, 3 element, multiple, Q-form, D
1775 // ASIMD load, 3 element, all lanes, D-form, B/H/S
1776 // ASIMD load, 3 element, all lanes, D-form, D
1777 // ASIMD load, 3 element, all lanes, Q-form, B/H/S
1778 // ASIMD load, 3 element, all lanes, Q-form, D
1784 // ASIMD load, 4 element, multiple, D-form, B/H/S
1785 // ASIMD load, 4 element, multiple, Q-form, B/H/S
1786 // ASIMD load, 4 element, multiple, Q-form, D
1800 // ASIMD load, 4 element, all lanes, D-form, B/H/S
1801 // ASIMD load, 4 element, all lanes, D-form, D
1802 // ASIMD load, 4 element, all lanes, Q-form, B/H/S
1803 // ASIMD load, 4 element, all lanes, Q-form, D
1809 //--
1811 //--
1813 // ASIMD store, 1 element, multiple, 1 reg, D-form
1814 // ASIMD store, 1 element, multiple, 1 reg, Q-form
1820 // ASIMD store, 1 element, multiple, 2 reg, D-form
1821 // ASIMD store, 1 element, multiple, 2 reg, Q-form
1827 // ASIMD store, 1 element, multiple, 3 reg, D-form
1828 // ASIMD store, 1 element, multiple, 3 reg, Q-form
1834 // ASIMD store, 1 element, multiple, 4 reg, D-form
1835 // ASIMD store, 1 element, multiple, 4 reg, Q-form
1848 // ASIMD store, 2 element, multiple, D-form, B/H/S
1849 // ASIMD store, 2 element, multiple, Q-form, B/H/S
1850 // ASIMD store, 2 element, multiple, Q-form, D
1863 // ASIMD store, 3 element, multiple, D-form, B/H/S
1864 // ASIMD store, 3 element, multiple, Q-form, B/H/S
1865 // ASIMD store, 3 element, multiple, Q-form, D
1879 // ASIMD store, 4 element, multiple, D-form, B/H/S
1880 // ASIMD store, 4 element, multiple, Q-form, B/H/S
1881 // ASIMD store, 4 element, multiple, Q-form, D