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1 //==- AArch64SchedThunderX.td - Cavium ThunderX T8X Scheduling Definitions -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 // Loosely based on Cortex-A53 which is somewhat similar.
13 //===----------------------------------------------------------------------===//
15 // ===---------------------------------------------------------------------===//
16 // The following definitions describe the simpler per-operand machine model.
21   let IssueWidth = 2;         // 2 micro-ops dispatched per cycle.
22   let MicroOpBufferSize = 0;  // ThunderX T88/T81/T83 are in-order.
24   let MispredictPenalty = 8;  // Branch mispredict penalty.
36 // Modeling each pipeline with BufferSize == 0 since T8X is in-order.
37 def THXT8XUnitALU    : ProcResource<2> { let BufferSize = 0; } // Int ALU
45 //===----------------------------------------------------------------------===//
46 // Subtarget-specific SchedWrite types mapping the ProcResources and
54 def : WriteRes<WriteISReg, [THXT8XUnitALU]> { let Latency = 2; }
55 def : WriteRes<WriteIEReg, [THXT8XUnitALU]> { let Latency = 2; }
56 def : WriteRes<WriteIS, [THXT8XUnitALU]> { let Latency = 2; }
57 def : WriteRes<WriteExtr, [THXT8XUnitALU]> { let Latency = 2; }
78   let ReleaseAtCycles = [8];
88   let Latency = 8;
104   let ReleaseAtCycles = [8];
190 //===----------------------------------------------------------------------===//
191 // Subtarget-specific SchedRead types.
195 def : ReadAdvance<ReadAdrBase, 2>;
196 def : ReadAdvance<ReadVLD, 2>;
197 def : ReadAdvance<ReadST, 2>;
200 // ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable
205 def : ReadAdvance<ReadI, 2, [WriteImm, WriteI,
213 def THXT8XReadNotShifted : SchedReadAdvance<2, [WriteImm, WriteI,
227 // MAC - Operands are generally needed one cycle later in the MAC pipe.
233 def : ReadAdvance<ReadIMA, 2, [WriteImm, WriteI,
244 //===----------------------------------------------------------------------===//
245 // Subtarget-specific InstRW.
247 //---
249 //---
260 //---
262 //---
265 //---
267 //---
270 //---
272 //---
273 def : InstRW<[THXT8XWriteVLD1], (instregex "LD1i(8|16|32|64)$")>;
274 def : InstRW<[THXT8XWriteVLD1], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
275 def : InstRW<[THXT8XWriteVLD1], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
276 def : InstRW<[THXT8XWriteVLD2], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
277 def : InstRW<[THXT8XWriteVLD3], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
278 def : InstRW<[THXT8XWriteVLD4], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
279 def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>;
280 def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
281 def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
282 def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
283 def : InstRW<[THXT8XWriteVLD3, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
284 def : InstRW<[THXT8XWriteVLD4, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
286 def : InstRW<[THXT8XWriteVLD1], (instregex "LD2i(8|16|32|64)$")>;
287 def : InstRW<[THXT8XWriteVLD1], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
288 def : InstRW<[THXT8XWriteVLD2], (instregex "LD2Twov(8b|4h|2s)$")>;
289 def : InstRW<[THXT8XWriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
290 def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD2i(8|16|32|64)(_POST)?$")>;
291 def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
292 def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD2Twov(8b|4h|2s)(_POST)?$")>;
293 def : InstRW<[THXT8XWriteVLD4, WriteAdr], (instregex "LD2Twov(16b|8h|4s|2d)(_POST)?$")>;
295 def : InstRW<[THXT8XWriteVLD2], (instregex "LD3i(8|16|32|64)$")>;
296 def : InstRW<[THXT8XWriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
297 def : InstRW<[THXT8XWriteVLD4], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)$")>;
298 def : InstRW<[THXT8XWriteVLD3], (instregex "LD3Threev(2d)$")>;
299 def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD3i(8|16|32|64)_POST$")>;
300 def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
301 def : InstRW<[THXT8XWriteVLD4, WriteAdr], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
302 def : InstRW<[THXT8XWriteVLD3, WriteAdr], (instregex "LD3Threev(2d)_POST$")>;
304 def : InstRW<[THXT8XWriteVLD2], (instregex "LD4i(8|16|32|64)$")>;
305 def : InstRW<[THXT8XWriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
306 def : InstRW<[THXT8XWriteVLD5], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>;
307 def : InstRW<[THXT8XWriteVLD4], (instregex "LD4Fourv(2d)$")>;
308 def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD4i(8|16|32|64)_POST$")>;
309 def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
310 def : InstRW<[THXT8XWriteVLD5, WriteAdr], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
311 def : InstRW<[THXT8XWriteVLD4, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>;
313 //---
315 //---
316 def : InstRW<[THXT8XWriteVST1], (instregex "ST1i(8|16|32|64)$")>;
317 def : InstRW<[THXT8XWriteVST1], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
318 def : InstRW<[THXT8XWriteVST1], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
319 def : InstRW<[THXT8XWriteVST2], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
320 def : InstRW<[THXT8XWriteVST2], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
321 def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST1i(8|16|32|64)_POST$")>;
322 def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
323 def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
324 def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
325 def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
327 def : InstRW<[THXT8XWriteVST1], (instregex "ST2i(8|16|32|64)$")>;
328 def : InstRW<[THXT8XWriteVST1], (instregex "ST2Twov(8b|4h|2s)$")>;
329 def : InstRW<[THXT8XWriteVST2], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
330 def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST2i(8|16|32|64)_POST$")>;
331 def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
332 def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
334 def : InstRW<[THXT8XWriteVST2], (instregex "ST3i(8|16|32|64)$")>;
335 def : InstRW<[THXT8XWriteVST3], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)$")>;
336 def : InstRW<[THXT8XWriteVST2], (instregex "ST3Threev(2d)$")>;
337 def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST3i(8|16|32|64)_POST$")>;
338 def : InstRW<[THXT8XWriteVST3, WriteAdr], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
339 def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST3Threev(2d)_POST$")>;
341 def : InstRW<[THXT8XWriteVST2], (instregex "ST4i(8|16|32|64)$")>;
342 def : InstRW<[THXT8XWriteVST3], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>;
343 def : InstRW<[THXT8XWriteVST2], (instregex "ST4Fourv(2d)$")>;
344 def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST4i(8|16|32|64)_POST$")>;
345 def : InstRW<[THXT8XWriteVST3, WriteAdr], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
346 def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>;
348 //---
350 //---