Lines Matching +full:pre +full:- +full:multiply
1 //==- AArch64SchedTSV110.td - Huawei TSV110 Scheduling Definitions -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 // ===---------------------------------------------------------------------===//
15 // The following definitions describe the simpler per-operand machine model.
20 let IssueWidth = 4; // 4 micro-ops dispatched per cycle.
21 let MicroOpBufferSize = 128; // 128 micro-op re-order buffer
34 // which has 8 pipelines, each with its own queue where micro-ops wait for
35 // their operands and issue out-of-order to one of eight execution pipelines.
39 def TSV110UnitMDU : ProcResource<1>; // Multi-Cycle
52 //===----------------------------------------------------------------------===//
53 // Map the target-defined scheduler read/write resources and latency for TSV110
80 // Pre/Post Indexing
112 // Forwarding logic is modeled only for multiply and accumulate.
127 //===----------------------------------------------------------------------===//
138 // 1 micro-ops to be issued down one ALU pipe, six MDU pipes and four LdSt pipes.
141 //===----------------------------------------------------------------------===//
142 // Define Generic 1 micro-op types
195 //===----------------------------------------------------------------------===//
196 // Define Generic 2 micro-op types
283 //===----------------------------------------------------------------------===//
284 // Define Generic 3 micro-op types
304 //===----------------------------------------------------------------------===//
305 // Define Generic 4 micro-op types
319 //===----------------------------------------------------------------------===//
320 // Define Generic 5 micro-op types
328 //===----------------------------------------------------------------------===//
329 // Define Generic 8 micro-op types
341 // -----------------------------------------------------------------------------
350 // -----------------------------------------------------------------------------
365 // -----------------------------------------------------------------------------
378 // ----------------------------------------------------------------------------
391 // ----------------------------------------------------------------------------
408 // -----------------------------------------------------------------------------
415 // Divide and Multiply Instructions
416 // -----------------------------------------------------------------------------
429 // Miscellaneous Data-Processing Instructions
430 // -----------------------------------------------------------------------------
438 // -----------------------------------------------------------------------------
446 def : InstRW<[WriteAdr, TSV110Wr_4cyc_1LdSt], (instregex "^LDR(BB|HH|W|X)(post|pre)$")>;
447 def : InstRW<[WriteAdr, TSV110Wr_4cyc_1LdSt], (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
456 def : InstRW<[WriteAdr, TSV110Wr_4cyc_1LdSt_1ALUAB, WriteLDHi],(instregex "^LDP(W|X)(post|pre)$")>;
469 // -----------------------------------------------------------------------------
472 def : InstRW<[WriteAdr, TSV110Wr_1cyc_1LdSt], (instregex "^STP(W|X)(post|pre)$")>;
477 def : InstRW<[WriteAdr, TSV110Wr_1cyc_1LdSt], (instregex "^STR(BB|HH|W|X)(post|pre)$")>;
482 // -----------------------------------------------------------------------------
512 // -----------------------------------------------------------------------------
523 // -----------------------------------------------------------------------------
527 def : InstRW<[WriteAdr, TSV110Wr_5cyc_1LdSt], (instregex "^LDR[BDHSQ](post|pre)")>;
531 def : InstRW<[WriteAdr, TSV110Wr_5cyc_1LdSt, WriteLDHi], (instregex "^LDP[DQS](post|pre)")>;
535 // -----------------------------------------------------------------------------
538 def : InstRW<[TSV110Wr_1cyc_1LdSt_1ALUAB, ReadAdrBase], (instregex "^STR[BHSDQ](post|pre)")>;
542 def : InstRW<[WriteAdr, TSV110Wr_2cyc_2LdSt], (instregex "^STP[SDQ](post|pre)")>;
546 // -----------------------------------------------------------------------------
549 // D form - v8i8, v4i16, v2i32
550 // Q form - v16i8, v8i16, v4i32
551 // D form - v1i8, v1i16, v1i32, v1i64
552 // Q form - v16i8, v8i16, v4i32, v2i64
553 // D form - v8i8_v8i16, v4i16_v4i32, v2i32_v2i64
554 // Q form - v16i8_v8i16, v8i16_v4i32, v4i32_v2i64
580 // ASIMD multiply accumulate, D-form
582 // ASIMD multiply accumulate, Q-form
585 // ASIMD multiply accumulate long
599 // ASIMD shift by register, basic, Q-form
601 // ASIMD shift by register, complex, D-form
603 // ASIMD shift by register, complex, Q-form
622 // Vector - Floating Point
623 // -----------------------------------------------------------------------------
626 // D form - v2f32
627 // Q form - v4f32, v2f64
628 // D form - 32, 64
629 // D form - v1i32, v1i64
630 // D form - v2i32
631 // Q form - v4i32, v2i64
645 // ASIMD FP divide, D-form, F32
647 // ASIMD FP divide, Q-form, F32
649 // ASIMD FP divide, Q-form, F64
665 // ASIMD FP multiply
670 // -----------------------------------------------------------------------------
685 // ASIMD table lookup, D-form
690 // ASIMD table lookup, Q-form
704 // -----------------------------------------------------------------------------
744 // -----------------------------------------------------------------------------