Lines Matching +full:micro +full:- +full:ab
1 //=- AArch64SchedNeoverseV2.td - NeoverseV2 Scheduling Defs --*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 // https://developer.arm.com/documentation/PJDOC-466751330-593177/r0p2
14 //===----------------------------------------------------------------------===//
17 let IssueWidth = 16; // Micro-ops dispatched at a time.
18 let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer.
21 let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
29 //===----------------------------------------------------------------------===//
31 // Instructions are first fetched and then decoded into internal macro-ops
33 // stages. A MOP can be split into two micro-ops further down the pipeline
34 // after the decode stage. Once dispatched, micro-ops wait for their operands
35 // and issue out-of-order to one of seventeen issue pipelines. Each issue
36 // pipeline can accept one micro-op per cycle.
42 def V2UnitS0 : ProcResource<1>; // Integer single-cycle 0
43 def V2UnitS1 : ProcResource<1>; // Integer single-cycle 1
44 def V2UnitS2 : ProcResource<1>; // Integer single-cycle 2
45 def V2UnitS3 : ProcResource<1>; // Integer single-cycle 3
56 def V2UnitR : ProcResGroup<[V2UnitS0, V2UnitS1]>; // Integer single-cycle 0/1
57 def V2UnitS : ProcResGroup<[V2UnitS0, V2UnitS1, V2UnitS2, V2UnitS3]>; // Integer single-cycle 0/…
58 def V2UnitF : ProcResGroup<[V2UnitS0, V2UnitS1, V2UnitM0, V2UnitM1]>; // Integer single-cycle 0/…
59 …itS0, V2UnitS1, V2UnitS2, V2UnitS3, V2UnitM0, V2UnitM1]>; // Integer single-cycle 0/1/2/3 and sin…
88 //===----------------------------------------------------------------------===//
91 //===----------------------------------------------------------------------===//
93 // Define generic 0 micro-op types
96 // Define generic 1 micro-op types
161 //===----------------------------------------------------------------------===//
162 // Define generic 2 micro-op types
384 //===----------------------------------------------------------------------===//
385 // Define generic 3 micro-op types
447 //===----------------------------------------------------------------------===//
448 // Define generic 4 micro-op types
574 //===----------------------------------------------------------------------===//
575 // Define generic 5 micro-op types
607 //===----------------------------------------------------------------------===//
608 // Define generic 6 micro-op types
670 //===----------------------------------------------------------------------===//
671 // Define generic 7 micro-op types
679 //===----------------------------------------------------------------------===//
680 // Define generic 8 micro-op types
716 //===----------------------------------------------------------------------===//
717 // Define generic 9 micro-op types
740 //===----------------------------------------------------------------------===//
741 // Define generic 10 micro-op types
750 //===----------------------------------------------------------------------===//
751 // Define generic 12 micro-op types
777 //===----------------------------------------------------------------------===//
778 // Define generic 16 micro-op types
800 //===----------------------------------------------------------------------===//
801 // Define generic 18 micro-op types
813 //===----------------------------------------------------------------------===//
814 // Define generic 27 micro-op types
830 //===----------------------------------------------------------------------===//
831 // Define generic 36 micro-op types
850 //===----------------------------------------------------------------------===//
851 // Define generic 54 micro-op types
881 //===----------------------------------------------------------------------===//
882 // Define predicate-controlled types
960 //===----------------------------------------------------------------------===//
1031 // NOTE: SOG p. 43: Complex multiply-add B, H, S element size: How to reduce
1071 //===----------------------------------------------------------------------===//
1087 // -----------------------------------------------------------------------------
1092 // -----------------------------------------------------------------------------
1106 // -----------------------------------------------------------------------------
1132 // Convert floating-point condition flags
1152 // -----------------------------------------------------------------------------
1157 // -----------------------------------------------------------------------------
1167 // Multiply accumulate, W-form
1168 // Multiply accumulate, X-form
1181 // -----------------------------------------------------------------------------
1199 def : InstRW<[V2Write_9cyc_1M0_1L], (instregex "^LDRA[AB](indexed|writeback)")>;
1204 // Miscellaneous data-processing instructions
1205 // -----------------------------------------------------------------------------
1222 // -----------------------------------------------------------------------------
1224 // NOTE: SOG p. 19: Throughput of LDN?P X-form should be 2, but reported as 3.
1235 // Load pair, immed post-index or immed pre-index, signed words
1240 // -----------------------------------------------------------------------------
1250 // -----------------------------------------------------------------------------
1257 // -----------------------------------------------------------------------------
1259 // Store allocation tags to one or two granules, post-index
1260 // Store allocation tags to one or two granules, pre-index
1261 // Store allocation tag to one or two granules, zeroing, post-index
1262 // Store Allocation Tag to one or two granules, zeroing, pre-index
1263 // Store allocation tag and reg pair to memory, post-Index
1264 // Store allocation tag and reg pair to memory, pre-Index
1279 // -----------------------------------------------------------------------------
1294 // FP divide, H-form
1296 // FP divide, S-form
1298 // FP divide, D-form
1301 // FP square root, H-form
1303 // FP square root, S-form
1305 // FP square root, D-form
1320 // -----------------------------------------------------------------------------
1351 // -----------------------------------------------------------------------------
1359 // Load vector reg, immed post-index
1360 // Load vector reg, immed pre-index
1368 // Load vector reg, register offset, scale, S/D-form
1369 // Load vector reg, register offset, scale, H/Q-form
1371 // Load vector reg, register offset, extend, scale, S/D-form
1372 // Load vector reg, register offset, extend, scale, H/Q-form
1375 // Load vector pair, immed offset, S/D-form
1378 // Load vector pair, immed offset, Q-form
1381 // Load vector pair, immed post-index, S/D-form
1382 // Load vector pair, immed pre-index, S/D-form
1386 // Load vector pair, immed post-index, Q-form
1387 // Load vector pair, immed pre-index, Q-form
1392 // -----------------------------------------------------------------------------
1394 // Store vector reg, unscaled immed, B/H/S/D-form
1395 // Store vector reg, unscaled immed, Q-form
1398 // Store vector reg, immed post-index, B/H/S/D-form
1399 // Store vector reg, immed post-index, Q-form
1400 // Store vector reg, immed pre-index, B/H/S/D-form
1401 // Store vector reg, immed pre-index, Q-form
1405 // Store vector reg, unsigned immed, B/H/S/D-form
1406 // Store vector reg, unsigned immed, Q-form
1409 // Store vector reg, register offset, basic, B/H/S/D-form
1410 // Store vector reg, register offset, basic, Q-form
1411 // Store vector reg, register offset, scale, H-form
1412 // Store vector reg, register offset, scale, S/D-form
1413 // Store vector reg, register offset, scale, Q-form
1414 // Store vector reg, register offset, extend, B/H/S/D-form
1415 // Store vector reg, register offset, extend, Q-form
1416 // Store vector reg, register offset, extend, scale, H-form
1417 // Store vector reg, register offset, extend, scale, S/D-form
1418 // Store vector reg, register offset, extend, scale, Q-form
1422 // Store vector pair, immed offset, S-form
1423 // Store vector pair, immed offset, D-form
1426 // Store vector pair, immed offset, Q-form
1429 // Store vector pair, immed post-index, S-form
1430 // Store vector pair, immed post-index, D-form
1431 // Store vector pair, immed pre-index, S-form
1432 // Store vector pair, immed pre-index, D-form
1436 // Store vector pair, immed post-index, Q-form
1439 // Store vector pair, immed pre-index, Q-form
1443 // -----------------------------------------------------------------------------
1449 // ASIMD arith, pair-wise
1452 // ASIMD max/min, basic and pair-wise
1475 // ASIMD matrix multiply-accumulate
1504 // ASIMD multiply/multiply long (8x8) polynomial, D-form
1505 // ASIMD multiply/multiply long (8x8) polynomial, Q-form
1540 // ASIMD floating-point instructions
1541 // -----------------------------------------------------------------------------
1568 // ASIMD FP convert, other, D-form F32 and Q-form F64
1576 // ASIMD FP convert, other, D-form F16 and Q-form F32
1584 // ASIMD FP convert, other, Q-form F16
1592 // ASIMD FP divide, D-form, F16
1595 // ASIMD FP divide, D-form, F32
1598 // ASIMD FP divide, Q-form, F16
1601 // ASIMD FP divide, Q-form, F32
1604 // ASIMD FP divide, Q-form, F64
1607 // ASIMD FP max/min, reduce, F32 and D-form F16
1610 // ASIMD FP max/min, reduce, Q-form F16
1622 // ASIMD FP round, D-form F32 and Q-form F64
1627 // ASIMD FP round, D-form F16 and Q-form F32
1632 // ASIMD FP round, Q-form F16
1635 // ASIMD FP square root, D-form, F16
1638 // ASIMD FP square root, D-form, F32
1641 // ASIMD FP square root, Q-form, F16
1644 // ASIMD FP square root, Q-form, F32
1647 // ASIMD FP square root, Q-form, F64
1651 // -----------------------------------------------------------------------------
1670 // -----------------------------------------------------------------------------
1694 // ASIMD reciprocal and square root estimate, D-form U32
1697 // ASIMD reciprocal and square root estimate, Q-form U32
1700 // ASIMD reciprocal and square root estimate, D-form F32 and scalar forms
1706 // ASIMD reciprocal and square root estimate, D-form F16 and Q-form F32
1710 // ASIMD reciprocal and square root estimate, Q-form F16
1746 // -----------------------------------------------------------------------------
1748 // ASIMD load, 1 element, multiple, 1 reg, D-form
1753 // ASIMD load, 1 element, multiple, 1 reg, Q-form
1758 // ASIMD load, 1 element, multiple, 2 reg, D-form
1763 // ASIMD load, 1 element, multiple, 2 reg, Q-form
1768 // ASIMD load, 1 element, multiple, 3 reg, D-form
1773 // ASIMD load, 1 element, multiple, 3 reg, Q-form
1778 // ASIMD load, 1 element, multiple, 4 reg, D-form
1783 // ASIMD load, 1 element, multiple, 4 reg, Q-form
1793 // ASIMD load, 1 element, all lanes, D-form, B/H/S
1794 // ASIMD load, 1 element, all lanes, D-form, D
1798 // ASIMD load, 1 element, all lanes, Q-form
1802 // ASIMD load, 2 element, multiple, D-form, B/H/S
1806 // ASIMD load, 2 element, multiple, Q-form, B/H/S
1807 // ASIMD load, 2 element, multiple, Q-form, D
1817 // ASIMD load, 2 element, all lanes, D-form, B/H/S
1818 // ASIMD load, 2 element, all lanes, D-form, D
1822 // ASIMD load, 2 element, all lanes, Q-form
1826 // ASIMD load, 3 element, multiple, D-form, B/H/S
1830 // ASIMD load, 3 element, multiple, Q-form, B/H/S
1831 // ASIMD load, 3 element, multiple, Q-form, D
1841 // ASIMD load, 3 element, all lanes, D-form, B/H/S
1842 // ASIMD load, 3 element, all lanes, D-form, D
1846 // ASIMD load, 3 element, all lanes, Q-form, B/H/S
1847 // ASIMD load, 3 element, all lanes, Q-form, D
1851 // ASIMD load, 4 element, multiple, D-form, B/H/S
1855 // ASIMD load, 4 element, multiple, Q-form, B/H/S
1856 // ASIMD load, 4 element, multiple, Q-form, D
1866 // ASIMD load, 4 element, all lanes, D-form, B/H/S
1867 // ASIMD load, 4 element, all lanes, D-form, D
1871 // ASIMD load, 4 element, all lanes, Q-form, B/H/S
1872 // ASIMD load, 4 element, all lanes, Q-form, D
1877 // -----------------------------------------------------------------------------
1879 // ASIMD store, 1 element, multiple, 1 reg, D-form
1883 // ASIMD store, 1 element, multiple, 1 reg, Q-form
1887 // ASIMD store, 1 element, multiple, 2 reg, D-form
1891 // ASIMD store, 1 element, multiple, 2 reg, Q-form
1895 // ASIMD store, 1 element, multiple, 3 reg, D-form
1899 // ASIMD store, 1 element, multiple, 3 reg, Q-form
1903 // ASIMD store, 1 element, multiple, 4 reg, D-form
1907 // ASIMD store, 1 element, multiple, 4 reg, Q-form
1916 // ASIMD store, 2 element, multiple, D-form, B/H/S
1920 // ASIMD store, 2 element, multiple, Q-form, B/H/S
1921 // ASIMD store, 2 element, multiple, Q-form, D
1930 // ASIMD store, 3 element, multiple, D-form, B/H/S
1934 // ASIMD store, 3 element, multiple, Q-form, B/H/S
1935 // ASIMD store, 3 element, multiple, Q-form, D
1945 // ASIMD store, 4 element, multiple, D-form, B/H/S
1949 // ASIMD store, 4 element, multiple, Q-form, B/H/S
1953 // ASIMD store, 4 element, multiple, Q-form, D
1966 // -----------------------------------------------------------------------------
1993 "^SM3TT[12][AB]$")>;
1999 // -----------------------------------------------------------------------------
2004 // -----------------------------------------------------------------------------
2086 // -----------------------------------------------------------------------------
2190 // Complex dot product 8-bit element
2193 // Complex dot product 16-bit element
2196 // Complex multiply-add B, H, S element size
2200 // Complex multiply-add D element size
2204 def : InstRW<[V2Write_8cyc_1M0_1V01], (instregex "^CLAST[AB]_RPZ_[BHSD]")>;
2207 def : InstRW<[V2Write_3cyc_1V1], (instregex "^CLAST[AB]_[VZ]PZ_[BHSD]",
2265 def : InstRW<[V2Write_3cyc_1V1], (instregex "^LAST[AB]_VPZ_[BHSD]",
2269 def : InstRW<[V2Write_6cyc_1V1_1M0], (instregex "^LAST[AB]_RPZ_[BHSD]",
2308 // Matrix multiply-accumulate
2431 // SVE floating-point instructions
2432 // -----------------------------------------------------------------------------
2591 // -----------------------------------------------------------------------------
2606 // -----------------------------------------------------------------------------
2640 // Non temporal gather load, vector + scalar 32-bit element size
2644 // Non temporal gather load, vector + scalar 64-bit element size
2678 // Gather load, vector + imm, 32-bit element size
2682 // Gather load, vector + imm, 64-bit element size
2686 // Gather load, 32-bit scaled offset
2691 // Gather load, 64-bit scaled offset
2697 // Gather load, 32-bit unpacked unscaled offset
2701 // Gather load, 64-bit unpacked unscaled offset
2708 // -----------------------------------------------------------------------------
2754 // Scatter non temporal store, vector + scalar 32-bit element size
2757 // Scatter non temporal store, vector + scalar 64-bit element size
2760 // Scatter store vector + imm 32-bit element size
2764 // Scatter store vector + imm 64-bit element size
2768 // Scatter store, 32-bit scaled offset
2772 // Scatter store, 32-bit unpacked unscaled offset
2776 // Scatter store, 32-bit unpacked scaled offset
2780 // Scatter store, 32-bit unscaled offset
2784 // Scatter store, 64-bit scaled offset
2788 // Scatter store, 64-bit unscaled offset
2793 // -----------------------------------------------------------------------------
2813 // -----------------------------------------------------------------------------