Lines Matching +full:micro +full:- +full:ab
1 //=- AArch64SchedNeoverseV1.td - NeoverseV1 Scheduling Model -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 // - "Arm Neoverse V1 Software Optimization Guide"
13 // - "Arm Neoverse V1 Platform: Unleashing a new performance tier for Arm-based computing"
14 …//community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/neoverse-v1-plat…
15 // - "Neoverse V1"
19 //===----------------------------------------------------------------------===//
22 let IssueWidth = 15; // Maximum micro-ops dispatch rate.
23 let MicroOpBufferSize = 256; // Micro-op re-order buffer.
26 let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
35 //===----------------------------------------------------------------------===//
37 // Instructions are first fetched and then decoded into internal macro-ops
39 // stages. A MOP can be split into one or more micro-ops further down the
40 // pipeline, after the decode stage. Once dispatched, micro-ops wait for their
41 // operands and issue out-of-order to one of the issue pipelines. Each issue
42 // pipeline can accept one micro-op per cycle.
61 def V1UnitJ : ProcResGroup<[V1UnitS, V1UnitM0]>; // Integer 0-2 units
89 //===----------------------------------------------------------------------===//
90 // Define generic 0 micro-op types
96 //===----------------------------------------------------------------------===//
97 // Define generic 1 micro-op types
162 //===----------------------------------------------------------------------===//
163 // Define generic 2 micro-op types
240 //===----------------------------------------------------------------------===//
241 // Define generic 3 micro-op types
266 //===----------------------------------------------------------------------===//
267 // Define generic 4 micro-op types
316 //===----------------------------------------------------------------------===//
317 // Define generic 5 micro-op types
335 //===----------------------------------------------------------------------===//
336 // Define generic 6 micro-op types
364 //===----------------------------------------------------------------------===//
365 // Define generic 7 micro-op types
375 //===----------------------------------------------------------------------===//
376 // Define generic 8 micro-op types
399 //===----------------------------------------------------------------------===//
400 // Define generic 10 micro-op types
419 //===----------------------------------------------------------------------===//
420 // Define generic 12 micro-op types
428 //===----------------------------------------------------------------------===//
429 // Define generic 15 micro-op types
440 //===----------------------------------------------------------------------===//
441 // Define generic 18 micro-op types
458 //===----------------------------------------------------------------------===//
459 // Define generic 27 micro-op types
474 // -----------------------------------------------------------------------------
484 // -----------------------------------------------------------------------------
502 // -----------------------------------------------------------------------------
550 // -----------------------------------------------------------------------------
571 // -----------------------------------------------------------------------------
584 def : InstRW<[V1Write_6c_1B_1M0], (instregex "^BL?RA[AB]Z?$",
585 "^E?RETA[AB]$")>;
588 def : InstRW<[V1Write_9c_1M0_1L], (instregex "^LDRA[AB](indexed|writeback)")>;
594 // Miscellaneous data-processing instructions
595 // -----------------------------------------------------------------------------
616 // -----------------------------------------------------------------------------
634 // Load pair, immed post or pre-index, signed words
640 // -----------------------------------------------------------------------------
653 // -----------------------------------------------------------------------------
668 // FP divide, H-form
669 // FP square root, H-form
672 // FP divide, S-form
673 // FP square root, S-form
676 // FP divide, D-form
679 // FP square root, D-form
697 // -----------------------------------------------------------------------------
728 // -----------------------------------------------------------------------------
737 // Load vector reg, immed post-index
738 // Load vector reg, immed pre-index
743 // Load vector reg, register offset, scale, S/D-form
745 // Load vector reg, register offset, extend, scale, S/D-form
748 // Load vector reg, register offset, scale, H/Q-form
749 // Load vector reg, register offset, extend, scale, H/Q-form
752 // Load vector pair, immed offset, S/D-form
755 // Load vector pair, immed offset, Q-form
758 // Load vector pair, immed post-index, S/D-form
759 // Load vector pair, immed pre-index, S/D-form
763 // Load vector pair, immed post-index, Q-form
764 // Load vector pair, immed pre-index, Q-form
770 // -----------------------------------------------------------------------------
772 // Store vector reg, unscaled immed, B/H/S/D/Q-form
775 // Store vector reg, immed post-index, B/H/S/D/Q-form
776 // Store vector reg, immed pre-index, B/H/S/D/Q-form
780 // Store vector reg, unsigned immed, B/H/S/D/Q-form
783 // Store vector reg, register offset, basic, B/S/D-form
784 // Store vector reg, register offset, scale, B/S/D-form
785 // Store vector reg, register offset, extend, B/S/D-form
786 // Store vector reg, register offset, extend, scale, B/S/D-form
790 // Store vector reg, register offset, basic, H/Q-form
791 // Store vector reg, register offset, scale, H/Q-form
792 // Store vector reg, register offset, extend, H/Q-form
793 // Store vector reg, register offset, extend, scale, H/Q-form
797 // Store vector pair, immed offset, S/D/Q-form
800 // Store vector pair, immed post-index, S/D-form
801 // Store vector pair, immed pre-index, S/D-form
805 // Store vector pair, immed post-index, Q-form
806 // Store vector pair, immed pre-index, Q-form
811 // -----------------------------------------------------------------------------
817 // ASIMD arith, pair-wise
820 // ASIMD max/min, basic and pair-wise
848 // ASIMD matrix multiply- accumulate
888 // -----------------------------------------------------------------------------
917 // ASIMD FP convert, other, D-form F32 and Q-form F64
921 // ASIMD FP convert, other, D-form F16 and Q-form F32
925 // ASIMD FP convert, other, Q-form F16
929 // ASIMD FP divide, D-form, F16
930 // ASIMD FP square root, D-form, F16
938 // ASIMD FP divide, Q-form, F16
941 // ASIMD FP divide, Q-form, F64
944 // ASIMD FP square root, Q-form, F16
947 // ASIMD FP square root, Q-form, F64
950 // ASIMD FP max/min, reduce, F32 and D-form F16
953 // ASIMD FP max/min, reduce, Q-form F16
962 // ASIMD FP round, D-form F32 and Q-form F64
965 // ASIMD FP round, D-form F16 and Q-form F32
968 // ASIMD FP round, Q-form F16
973 // -----------------------------------------------------------------------------
992 // -----------------------------------------------------------------------------
1018 // ASIMD reciprocal and square root estimate, D-form U32
1019 // ASIMD reciprocal and square root estimate, D-form F32 and F64
1025 // ASIMD reciprocal and square root estimate, Q-form U32
1026 // ASIMD reciprocal and square root estimate, D-form F16 and Q-form F32 and F64
1034 // ASIMD reciprocal and square root estimate, Q-form F16
1073 // -----------------------------------------------------------------------------
1093 // ASIMD load, 1 element, multiple, 4 reg, D-form
1099 // ASIMD load, 1 element, multiple, 4 reg, Q-form
1114 // ASIMD load, 2 element, multiple, D-form
1120 // ASIMD load, 2 element, multiple, Q-form
1135 // ASIMD load, 3 element, multiple, D-form
1147 // ASIMD load, 3 element, multiple, Q-form
1153 // ASIMD load, 4 element, multiple, D-form
1165 // ASIMD load, 4 element, multiple, Q-form
1173 // -----------------------------------------------------------------------------
1176 // ASIMD store, 1 element, multiple, 2 reg, D-form
1184 // ASIMD store, 1 element, multiple, 2 reg, Q-form
1185 // ASIMD store, 1 element, multiple, 3 reg, D-form
1186 // ASIMD store, 1 element, multiple, 4 reg, D-form
1196 // ASIMD store, 1 element, multiple, 3 reg, Q-form
1202 // ASIMD store, 1 element, multiple, 4 reg, Q-form
1209 // ASIMD store, 2 element, multiple, D-form
1220 // ASIMD store, 2 element, multiple, Q-form
1221 // ASIMD store, 3 element, multiple, D-form
1235 // ASIMD store, 3 element, multiple, Q-form
1241 // ASIMD store, 4 element, multiple, D-form
1247 // ASIMD store, 4 element, multiple, Q-form, B/H/S
1253 // ASIMD store, 4 element, multiple, Q-form, D
1267 // -----------------------------------------------------------------------------
1286 "^SM3(PARTW(1|2SM3SS1)|TT[12][AB])$")>;
1300 // -----------------------------------------------------------------------------
1307 // -----------------------------------------------------------------------------
1310 def : InstRW<[V1Write_2c_1M0], (instregex "^BRK[AB]_PP[mz]P$")>;
1370 // -----------------------------------------------------------------------------
1411 def : InstRW<[V1Write_9c_1M0_1V1], (instregex "^CLAST[AB]_RPZ_[BHSD]$")>;
1414 def : InstRW<[V1Write_3c_1V1], (instregex "^CLAST[AB]_[VZ]PZ_[BHSD]$",
1467 def : InstRW<[V1Write_3c_1V1], (instregex "^LAST[AB]_VPZ_[BHSD]$",
1471 def : InstRW<[V1Write_6c_1M0_1V1], (instregex "^LAST[AB]_RPZ_[BHSD]$",
1490 // Matrix multiply-accumulate
1552 // SVE floating-point instructions
1553 // -----------------------------------------------------------------------------
1678 // -----------------------------------------------------------------------------
1694 // -----------------------------------------------------------------------------
1763 // Gather load, vector + imm, 32-bit element size
1767 // Gather load, vector + imm, 64-bit element size
1774 // Gather load, 32-bit scaled offset
1779 // Gather load, 32-bit unpacked unscaled offset
1790 // -----------------------------------------------------------------------------
1833 // Scatter store vector + imm 32-bit element size
1834 // Scatter store, 32-bit scaled offset
1835 // Scatter store, 32-bit unscaled offset
1842 // Scatter store, 32-bit unpacked unscaled offset
1843 // Scatter store, 32-bit unpacked scaled offset
1849 // Scatter store vector + imm 64-bit element size
1850 // Scatter store, 64-bit scaled offset
1851 // Scatter store, 64-bit unscaled offset
1861 // -----------------------------------------------------------------------------