Lines Matching +full:micro +full:- +full:ab
1 //=- AArch64SchedNeoverseN2.td - NeoverseN2 Scheduling Defs --*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 let IssueWidth = 10; // Micro-ops dispatched at a time.
15 let MicroOpBufferSize = 160; // Entries in micro-op re-order buffer.
18 let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
25 //===----------------------------------------------------------------------===//
27 // Instructions are first fetched and then decoded into internal macro-ops
29 // stages. A MOP can be split into two micro-ops further down the pipeline
30 // after the decode stage. Once dispatched, micro-ops wait for their operands
31 // and issue out-of-order to one of thirteen issue pipelines. Each issue
32 // pipeline can accept one micro-op per cycle.
71 //===----------------------------------------------------------------------===//
74 //===----------------------------------------------------------------------===//
75 // Define generic 1 micro-op types
120 //===----------------------------------------------------------------------===//
121 // Define generic 2 micro-op types
302 //===----------------------------------------------------------------------===//
303 // Define generic 3 micro-op types
355 //===----------------------------------------------------------------------===//
356 // Define generic 4 micro-op types
458 //===----------------------------------------------------------------------===//
459 // Define generic 5 micro-op types
473 //===----------------------------------------------------------------------===//
474 // Define generic 6 micro-op types
506 //===----------------------------------------------------------------------===//
507 // Define generic 7 micro-op types
515 //===----------------------------------------------------------------------===//
516 // Define generic 8 micro-op types
550 //===----------------------------------------------------------------------===//
551 // Define generic 10 micro-op types
560 //===----------------------------------------------------------------------===//
561 // Define generic 12 micro-op types
571 //===----------------------------------------------------------------------===//
572 // Define generic 15 micro-op types
583 //===----------------------------------------------------------------------===//
584 // Define generic 18 micro-op types
596 //===----------------------------------------------------------------------===//
597 // Define generic 27 micro-op types
612 //===----------------------------------------------------------------------===//
623 // -----------------------------------------------------------------------------
628 // -----------------------------------------------------------------------------
642 // -----------------------------------------------------------------------------
666 // Convert floating-point condition flags
679 // -----------------------------------------------------------------------------
684 // -----------------------------------------------------------------------------
697 // -----------------------------------------------------------------------------
715 def : InstRW<[N2Write_9cyc_1M0_1L], (instregex "^LDRA[AB](indexed|writeback)")>;
720 // Miscellaneous data-processing instructions
721 // -----------------------------------------------------------------------------
737 // -----------------------------------------------------------------------------
744 // Load pair, immed post-index or immed pre-index, signed words
749 // -----------------------------------------------------------------------------
757 // -----------------------------------------------------------------------------
764 // -----------------------------------------------------------------------------
766 // Store allocation tags to one or two granules, post-index
767 // Store allocation tags to one or two granules, pre-index
768 // Store allocation tag to one or two granules, zeroing, post-index
769 // Store Allocation Tag to one or two granules, zeroing, pre-index
770 // Store allocation tag and reg pair to memory, post-Index
771 // Store allocation tag and reg pair to memory, pre-Index
786 // -----------------------------------------------------------------------------
801 // FP divide, H-form
803 // FP divide, S-form
805 // FP divide, D-form
808 // FP square root, H-form
810 // FP square root, S-form
812 // FP square root, D-form
826 // -----------------------------------------------------------------------------
853 // -----------------------------------------------------------------------------
860 // Load vector reg, immed post-index
862 // Load vector reg, immed pre-index
869 // Load vector reg, register offset, scale, S/D-form
871 // Load vector reg, register offset, extend, scale, S/D-form
874 // Load vector reg, register offset, scale, H/Q-form
875 // Load vector reg, register offset, extend, scale, H/Q-form
878 // Load vector pair, immed offset, S/D-form
881 // Load vector pair, immed offset, Q-form
884 // Load vector pair, immed post-index, S/D-form
885 // Load vector pair, immed pre-index, S/D-form
889 // Load vector pair, immed post-index, Q-form
890 // Load vector pair, immed pre-index, Q-form
895 // -----------------------------------------------------------------------------
897 // Store vector reg, unscaled immed, B/H/S/D-form
898 // Store vector reg, unscaled immed, Q-form
901 // Store vector reg, immed post-index, B/H/S/D-form
902 // Store vector reg, immed post-index, Q-form
903 // Store vector reg, immed pre-index, B/H/S/D-form
904 // Store vector reg, immed pre-index, Q-form
908 // Store vector reg, unsigned immed, B/H/S/D-form
909 // Store vector reg, unsigned immed, Q-form
912 // Store vector reg, register offset, basic, B/H/S/D-form
913 // Store vector reg, register offset, basic, Q-form
914 // Store vector reg, register offset, scale, S/D-form
915 // Store vector reg, register offset, extend, B/H/S/D-form
916 // Store vector reg, register offset, extend, Q-form
917 // Store vector reg, register offset, extend, scale, S/D-form
921 // Store vector reg, register offset, scale, H-form
922 // Store vector reg, register offset, scale, Q-form
923 // Store vector reg, register offset, extend, scale, H-form
924 // Store vector reg, register offset, extend, scale, Q-form
928 // Store vector pair, immed offset, S-form
929 // Store vector pair, immed offset, D-form
932 // Store vector pair, immed offset, Q-form
935 // Store vector pair, immed post-index, S-form
936 // Store vector pair, immed post-index, D-form
937 // Store vector pair, immed pre-index, S-form
938 // Store vector pair, immed pre-index, D-form
942 // Store vector pair, immed post-index, Q-form
945 // Store vector pair, immed pre-index, Q-form
949 // -----------------------------------------------------------------------------
955 // ASIMD arith, pair-wise
958 // ASIMD max/min, basic and pair-wise
983 // ASIMD matrix multiply-accumulate
1012 // ASIMD multiply/multiply long (8x8) polynomial, D-form
1013 // ASIMD multiply/multiply long (8x8) polynomial, Q-form
1049 // ASIMD floating-point instructions
1050 // -----------------------------------------------------------------------------
1077 // ASIMD FP convert, other, D-form F32 and Q-form F64
1081 // ASIMD FP convert, other, D-form F16 and Q-form F32
1085 // ASIMD FP convert, other, Q-form F16
1089 // ASIMD FP divide, D-form, F16
1092 // ASIMD FP divide, D-form, F32
1095 // ASIMD FP divide, Q-form, F16
1098 // ASIMD FP divide, Q-form, F32
1101 // ASIMD FP divide, Q-form, F64
1104 // ASIMD FP max/min, reduce, F32 and D-form F16
1107 // ASIMD FP max/min, reduce, Q-form F16
1119 // ASIMD FP round, D-form F32 and Q-form F64
1124 // ASIMD FP round, D-form F16 and Q-form F32
1130 // ASIMD FP round, Q-form F16
1133 // ASIMD FP square root, D-form, F16
1136 // ASIMD FP square root, D-form, F32
1139 // ASIMD FP square root, Q-form, F16
1142 // ASIMD FP square root, Q-form, F32
1145 // ASIMD FP square root, Q-form, F64
1149 // -----------------------------------------------------------------------------
1168 // -----------------------------------------------------------------------------
1193 // ASIMD reciprocal and square root estimate, D-form U32
1196 // ASIMD reciprocal and square root estimate, Q-form U32
1199 // ASIMD reciprocal and square root estimate, D-form F32 and scalar forms
1205 // ASIMD reciprocal and square root estimate, D-form F16 and Q-form F32
1209 // ASIMD reciprocal and square root estimate, Q-form F16
1237 // -----------------------------------------------------------------------------
1239 // ASIMD load, 1 element, multiple, 1 reg, D-form
1244 // ASIMD load, 1 element, multiple, 1 reg, Q-form
1249 // ASIMD load, 1 element, multiple, 2 reg, D-form
1254 // ASIMD load, 1 element, multiple, 2 reg, Q-form
1259 // ASIMD load, 1 element, multiple, 3 reg, D-form
1264 // ASIMD load, 1 element, multiple, 3 reg, Q-form
1269 // ASIMD load, 1 element, multiple, 4 reg, D-form
1274 // ASIMD load, 1 element, multiple, 4 reg, Q-form
1284 // ASIMD load, 1 element, all lanes, D-form, B/H/S
1285 // ASIMD load, 1 element, all lanes, D-form, D
1289 // ASIMD load, 1 element, all lanes, Q-form
1293 // ASIMD load, 2 element, multiple, D-form, B/H/S
1297 // ASIMD load, 2 element, multiple, Q-form, B/H/S
1298 // ASIMD load, 2 element, multiple, Q-form, D
1308 // ASIMD load, 2 element, all lanes, D-form, B/H/S
1309 // ASIMD load, 2 element, all lanes, D-form, D
1313 // ASIMD load, 2 element, all lanes, Q-form
1317 // ASIMD load, 3 element, multiple, D-form, B/H/S
1321 // ASIMD load, 3 element, multiple, Q-form, B/H/S
1325 // ASIMD load, 3 element, multiple, Q-form, D
1335 // ASIMD load, 3 element, all lanes, D-form, B/H/S
1336 // ASIMD load, 3 element, all lanes, D-form, D
1340 // ASIMD load, 3 element, all lanes, Q-form, B/H/S
1341 // ASIMD load, 3 element, all lanes, Q-form, D
1345 // ASIMD load, 4 element, multiple, D-form, B/H/S
1349 // ASIMD load, 4 element, multiple, Q-form, B/H/S
1350 // ASIMD load, 4 element, multiple, Q-form, D
1360 // ASIMD load, 4 element, all lanes, D-form, B/H/S
1361 // ASIMD load, 4 element, all lanes, D-form, D
1365 // ASIMD load, 4 element, all lanes, Q-form, B/H/S
1366 // ASIMD load, 4 element, all lanes, Q-form, D
1371 // -----------------------------------------------------------------------------
1373 // ASIMD store, 1 element, multiple, 1 reg, D-form
1377 // ASIMD store, 1 element, multiple, 1 reg, Q-form
1381 // ASIMD store, 1 element, multiple, 2 reg, D-form
1385 // ASIMD store, 1 element, multiple, 2 reg, Q-form
1389 // ASIMD store, 1 element, multiple, 3 reg, D-form
1393 // ASIMD store, 1 element, multiple, 3 reg, Q-form
1397 // ASIMD store, 1 element, multiple, 4 reg, D-form
1401 // ASIMD store, 1 element, multiple, 4 reg, Q-form
1410 // ASIMD store, 2 element, multiple, D-form, B/H/S
1414 // ASIMD store, 2 element, multiple, Q-form, B/H/S
1415 // ASIMD store, 2 element, multiple, Q-form, D
1424 // ASIMD store, 3 element, multiple, D-form, B/H/S
1428 // ASIMD store, 3 element, multiple, Q-form, B/H/S
1429 // ASIMD store, 3 element, multiple, Q-form, D
1439 // ASIMD store, 4 element, multiple, D-form, B/H/S
1443 // ASIMD store, 4 element, multiple, Q-form, B/H/S
1447 // ASIMD store, 4 element, multiple, Q-form, D
1460 // -----------------------------------------------------------------------------
1487 "^SM3TT[12][AB]$")>;
1493 // -----------------------------------------------------------------------------
1498 // -----------------------------------------------------------------------------
1577 // -----------------------------------------------------------------------------
1679 // Complex dot product 8-bit element
1682 // Complex dot product 16-bit element
1685 // Complex multiply-add B, H, S element size
1689 // Complex multiply-add D element size
1693 def : InstRW<[N2Write_8cyc_1M0_1V1_1V], (instregex "^CLAST[AB]_RPZ_[BHSD]$")>;
1696 def : InstRW<[N2Write_3cyc_1V1], (instregex "^CLAST[AB]_[VZ]PZ_[BHSD]$",
1754 def : InstRW<[N2Write_3cyc_1V1], (instregex "^LAST[AB]_VPZ_[BHSD]$",
1758 def : InstRW<[N2Write_5cyc_1V1_1M0], (instregex "^LAST[AB]_RPZ_[BHSD]$",
1795 // Matrix multiply-accumulate
1914 // SVE floating-point instructions
1915 // -----------------------------------------------------------------------------
2071 // -----------------------------------------------------------------------------
2086 // -----------------------------------------------------------------------------
2122 // Non temporal gather load, vector + scalar 32-bit element size
2126 // Non temporal gather load, vector + scalar 64-bit element size
2160 // Gather load, vector + imm, 32-bit element size
2164 // Gather load, vector + imm, 64-bit element size
2168 // Gather load, 64-bit element size
2175 // Gather load, 32-bit scaled offset
2180 // Gather load, 32-bit unpacked unscaled offset
2185 // -----------------------------------------------------------------------------
2239 // Scatter non temporal store, vector + scalar 32-bit element size
2242 // Scatter non temporal store, vector + scalar 64-bit element size
2245 // Scatter store vector + imm 32-bit element size
2249 // Scatter store vector + imm 64-bit element size
2253 // Scatter store, 32-bit scaled offset
2257 // Scatter store, 32-bit unpacked unscaled offset
2261 // Scatter store, 32-bit unpacked scaled offset
2265 // Scatter store, 32-bit unscaled offset
2269 // Scatter store, 64-bit scaled offset
2273 // Scatter store, 64-bit unscaled offset
2278 // -----------------------------------------------------------------------------
2297 // -----------------------------------------------------------------------------