Lines Matching full:latency
136 def M4WriteZ0 : SchedWriteRes<[]> { let Latency = 0; }
137 def M4WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
139 def M4WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
142 def M4WriteA1 : SchedWriteRes<[M4UnitALU]> { let Latency = 1; }
143 def M4WriteA2 : SchedWriteRes<[M4UnitALU]> { let Latency = 2; }
144 def M4WriteAA : SchedWriteRes<[M4UnitALU]> { let Latency = 2;
147 M4UnitC]> { let Latency = 2;
151 M4UnitC]> { let Latency = 3;
154 M4UnitC]> { let Latency = 2;
156 def M4WriteAF : SchedWriteRes<[M4UnitALU]> { let Latency = 2;
172 def M4WriteB1 : SchedWriteRes<[M4UnitB]> { let Latency = 1; }
176 def M4WriteC1 : SchedWriteRes<[M4UnitC]> { let Latency = 1; }
177 def M4WriteC3 : SchedWriteRes<[M4UnitC]> { let Latency = 3; }
178 def M4WriteCA : SchedWriteRes<[M4UnitC]> { let Latency = 4;
181 def M4WriteD12 : SchedWriteRes<[M4UnitD]> { let Latency = 12;
183 def M4WriteD21 : SchedWriteRes<[M4UnitD]> { let Latency = 21;
186 def M4WriteE2 : SchedWriteRes<[M4UnitE]> { let Latency = 2; }
188 def M4WriteL4 : SchedWriteRes<[M4UnitL]> { let Latency = 4; }
189 def M4WriteL5 : SchedWriteRes<[M4UnitL]> { let Latency = 5; }
191 M4UnitL]> { let Latency = 5;
194 M4UnitL]> { let Latency = 5;
198 M4UnitL]> { let Latency = 5;
201 M4UnitL]> { let Latency = 4;
204 M4UnitL]> { let Latency = 6;
206 def M4WriteLH : SchedWriteRes<[]> { let Latency = 5;
213 def M4WriteS1 : SchedWriteRes<[M4UnitS]> { let Latency = 1; }
214 def M4WriteSA : SchedWriteRes<[M4UnitS0]> { let Latency = 3; }
216 M4UnitS]> { let Latency = 2;
229 M4UnitFADD]> { let Latency = 3;
232 M4UnitS0]> { let Latency = 5;
235 M4UnitFST]> { let Latency = 6;
238 M4UnitS0]> { let Latency = 5;
241 M4UnitS0]> { let Latency = 2;
244 M4UnitS0]> { let Latency = 4; }
247 M4UnitS0]> { let Latency = 5;
249 def M4WriteNEONL : SchedWriteRes<[M4UnitNMUL]> { let Latency = 3; }
251 M4UnitNMSC]> { let Latency = 5;
255 M4UnitNMSC]> { let Latency = 8;
258 M4UnitNMSC]> { let Latency = 4;
261 M4UnitC]> { let Latency = 3;
264 M4UnitS0]> { let Latency = 4;
267 M4UnitFDIV]> { let Latency = 7;
270 M4UnitFDIVH]> { let Latency = 7;
273 M4UnitFDIV]> { let Latency = 12;
276 M4UnitFSQR]> { let Latency = 8;
279 M4UnitFSQRH]> { let Latency = 7;
282 M4UnitFSQR]> { let Latency = 12;
287 def M4WriteFADD2 : SchedWriteRes<[M4UnitFADD]> { let Latency = 2; }
288 def M4WriteFADD2H : SchedWriteRes<[M4UnitFADDH]> { let Latency = 2; }
290 def M4WriteFCVT2 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 2; }
291 def M4WriteFCVT2A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 2; }
292 def M4WriteFCVT2H : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 2; }
293 def M4WriteFCVT3 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 3; }
294 def M4WriteFCVT3A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 3; }
295 def M4WriteFCVT3H : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 3; }
296 def M4WriteFCVT4 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 4; }
297 def M4WriteFCVT4A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 4; }
298 def M4WriteFCVT6A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 6; }
300 def M4WriteFDIV7 : SchedWriteRes<[M4UnitFDIV]> { let Latency = 7;
302 def M4WriteFDIV7H : SchedWriteRes<[M4UnitFDIVH]> { let Latency = 7;
304 def M4WriteFDIV12 : SchedWriteRes<[M4UnitFDIV]> { let Latency = 12;
307 def M4WriteFMAC2H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 2; }
308 def M4WriteFMAC3H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 3; }
309 def M4WriteFMAC3 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 3; }
310 def M4WriteFMAC4 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 4; }
311 def M4WriteFMAC4H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 4; }
313 def M4WriteFSQR7H : SchedWriteRes<[M4UnitFSQRH]> { let Latency = 7;
315 def M4WriteFSQR8 : SchedWriteRes<[M4UnitFSQR]> { let Latency = 8;
317 def M4WriteFSQR12 : SchedWriteRes<[M4UnitFSQR]> { let Latency = 12;
320 def M4WriteNALU1 : SchedWriteRes<[M4UnitNALU]> { let Latency = 1; }
321 def M4WriteNALU1H : SchedWriteRes<[M4UnitNALUH]> { let Latency = 1; }
323 def M4WriteNCRY1 : SchedWriteRes<[M4UnitNCRY]> { let Latency = 1; }
324 def M4WriteNCRY1A : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 1; }
325 def M4WriteNCRY3A : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 3; }
326 def M4WriteNCRY5A : SchedWriteRes<[M4UnitNCRY]> { let Latency = 5; }
328 def M4WriteNHAD1 : SchedWriteRes<[M4UnitNHAD]> { let Latency = 1; }
329 def M4WriteNHAD3 : SchedWriteRes<[M4UnitNHAD]> { let Latency = 3; }
331 def M4WriteNMSC1 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 1; }
332 def M4WriteNMSC2 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 2; }
333 def M4WriteNMSC3 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 3; }
335 def M4WriteNMUL3 : SchedWriteRes<[M4UnitNMUL]> { let Latency = 3; }
337 def M4WriteNSHF1 : SchedWriteRes<[M4UnitNSHF]> { let Latency = 1; }
338 def M4WriteNSHF1H : SchedWriteRes<[M4UnitNSHFH]> { let Latency = 1; }
339 def M4WriteNSHF3 : SchedWriteRes<[M4UnitNSHF]> { let Latency = 3; }
340 def M4WriteNSHFA : SchedWriteRes<[M4UnitNSHF]> { let Latency = 1;
342 def M4WriteNSHFB : SchedWriteRes<[M4UnitNSHF]> { let Latency = 2;
345 def M4WriteNSHFC : SchedWriteRes<[M4UnitNSHF]> { let Latency = 3;
348 def M4WriteNSHFD : SchedWriteRes<[M4UnitNSHF]> { let Latency = 4;
352 def M4WriteNSHT1 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 1; }
353 def M4WriteNSHT2 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 2; }
354 def M4WriteNSHT3 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 3; }
355 def M4WriteNSHT4A : SchedWriteRes<[M4UnitNSHT1]> { let Latency = 4; }
358 M4UnitL]> { let Latency = 5;
362 M4UnitL]> { let Latency = 6;
367 M4UnitL]> { let Latency = 6;
370 M4UnitNSHF]> { let Latency = 6;
374 M4UnitL]> { let Latency = 10;
379 M4UnitNSHF]> { let Latency = 6;
384 M4UnitL]> { let Latency = 12;
390 M4UnitNSHF]> { let Latency = 7;
397 M4UnitNSHF]> { let Latency = 7;
404 M4UnitNSHF]> { let Latency = 7;
412 M4UnitNSHF]> { let Latency = 7;
418 M4UnitL]> { let Latency = 14;
423 M4UnitFST]> { let Latency = 1;
429 M4UnitFST]> { let Latency = 2; }
433 M4UnitFST]> { let Latency = 2;
439 M4UnitFST]> { let Latency = 4;
450 M4UnitFST]> { let Latency = 5;
464 M4UnitFST]> { let Latency = 8;
471 M4UnitFST]> { let Latency = 1;
475 M4UnitFST]> { let Latency = 3;
482 M4UnitFST]> { let Latency = 4;
565 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
566 def : WriteRes<WriteHint, []> { let Latency = 1; }
567 def : WriteRes<WriteSys, []> { let Latency = 1; }