Lines Matching +full:pre +full:- +full:multiply
1 //=- AArch64SchedA64FX.td - Fujitsu A64FX Scheduling Defs -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 let IssueWidth = 6; // 6 micro-ops dispatched at a time.
15 let MicroOpBufferSize = 180; // 180 entries in micro-op re-order buffer.
18 // Determined via a mix of micro-arch details and experimentation.
550 //===----------------------------------------------------------------------===//
553 //---
555 //---
579 //---
581 //---
588 //---
591 //---
667 //---
668 // 3.4 Divide and Multiply Instructions
669 //---
671 // Divide, W-form
677 // Divide, X-form
683 // Multiply accumulate, W-form
688 // Multiply accumulate, X-form
706 // Multiply high
709 // Miscellaneous Data-Processing Instructions
713 // Bitifield move - basic
751 //---
754 //---
764 // Load register, immed post-index
766 // Load register, immed pre-index
775 // LDP only breaks into *one* LS micro-op. Thus
797 // Load pair, immed pre-index, normal
798 // Load pair, immed pre-index, signed words
799 // Load pair, immed post-index, normal
800 // Load pair, immed post-index, signed words
1009 //---
1011 //---
1018 //--
1021 //--
1030 // Store register, immed post-index
1033 // Store register, immed pre-index
1046 // Store pair, immed offset, W-form
1047 // Store pair, immed offset, X-form
1052 // Store pair, immed post-index, W-form
1053 // Store pair, immed post-index, X-form
1054 // Store pair, immed pre-index, W-form
1055 // Store pair, immed pre-index, X-form
1247 //---
1249 //---
1295 // FP divide, S-form
1296 // FP square root, S-form
1304 // FP divide, D-form
1305 // FP square root, D-form
1320 //---
1322 //---
1349 //---
1351 //---
1353 // ASIMD absolute diff, D-form
1354 // ASIMD absolute diff, Q-form
1355 // ASIMD absolute diff accum, D-form
1356 // ASIMD absolute diff accum, Q-form
1367 // ASIMD multiply, D-form
1368 // ASIMD multiply, Q-form
1369 // ASIMD multiply accumulate long
1370 // ASIMD multiply accumulate saturating long
1371 // ASIMD multiply long
1375 // ASIMD shift by immed and insert, basic, D-form
1376 // ASIMD shift by immed and insert, basic, Q-form
1378 // ASIMD shift by register, basic, D-form
1379 // ASIMD shift by register, basic, Q-form
1380 // ASIMD shift by register, complex, D-form
1381 // ASIMD shift by register, complex, Q-form
1401 // ASIMD polynomial (8x8) multiply long
1408 // ASIMD absolute diff accum, D-form
1411 // ASIMD absolute diff accum, Q-form
1435 // ASIMD multiply, D-form
1441 // ASIMD multiply, Q-form
1445 // ASIMD multiply, Q-form
1449 // ASIMD multiply accumulate, D-form
1452 // ASIMD multiply accumulate, Q-form
1473 // ASIMD shift by register, basic, Q-form
1476 // ASIMD shift by register, complex, D-form
1480 // ASIMD shift by register, complex, Q-form
1532 //---
1533 // 3.13 ASIMD Floating-point Instructions
1534 //---
1543 // ASIMD FP arith, normal, D-form
1544 // ASIMD FP arith, normal, Q-form
1548 // ASIMD FP arith, pairwise, D-form
1549 // ASIMD FP arith, pairwise, Q-form
1552 // ASIMD FP compare, D-form
1553 // ASIMD FP compare, Q-form
1558 // ASIMD FP round, D-form
1561 // ASIMD FP round, Q-form
1567 // ASIMD FP convert, other, D-form
1568 // ASIMD FP convert, other, Q-form
1572 // ASIMD FP convert, other, D-form
1575 // ASIMD FP convert, other, Q-form
1579 // ASIMD FP divide, D-form, F32
1583 // ASIMD FP divide, Q-form, F32
1587 // ASIMD FP divide, Q-form, F64
1591 // ASIMD FP max/min, normal, D-form
1592 // ASIMD FP max/min, normal, Q-form
1596 // ASIMD FP max/min, pairwise, D-form
1597 // ASIMD FP max/min, pairwise, Q-form
1605 // ASIMD FP multiply, D-form, FZ
1606 // ASIMD FP multiply, D-form, no FZ
1607 // ASIMD FP multiply, Q-form, FZ
1608 // ASIMD FP multiply, Q-form, no FZ
1615 // ASIMD FP multiply accumulate, Dform, FZ
1616 // ASIMD FP multiply accumulate, Dform, no FZ
1617 // ASIMD FP multiply accumulate, Qform, FZ
1618 // ASIMD FP multiply accumulate, Qform, no FZ
1628 //--
1630 //--
1635 // ASIMD bitwise insert, D-form
1636 // ASIMD bitwise insert, Q-form
1640 // ASIMD count, D-form
1641 // ASIMD count, Q-form
1673 // ASIMD table lookup, D-form
1683 // ASIMD table lookup, Q-form
1697 // ASIMD reciprocal estimate, D-form
1698 // ASIMD reciprocal estimate, Q-form
1703 // ASIMD reciprocal step, D-form, FZ
1704 // ASIMD reciprocal step, D-form, no FZ
1705 // ASIMD reciprocal step, Q-form, FZ
1706 // ASIMD reciprocal step, Q-form, no FZ
1713 // ASIMD table lookup, D-form
1714 // ASIMD table lookup, Q-form
1733 //--
1735 //--
1737 // ASIMD load, 1 element, multiple, 1 reg, D-form
1738 // ASIMD load, 1 element, multiple, 1 reg, Q-form
1748 // ASIMD load, 1 element, multiple, 2 reg, D-form
1749 // ASIMD load, 1 element, multiple, 2 reg, Q-form
1759 // ASIMD load, 1 element, multiple, 3 reg, D-form
1760 // ASIMD load, 1 element, multiple, 3 reg, Q-form
1770 // ASIMD load, 1 element, multiple, 4 reg, D-form
1771 // ASIMD load, 1 element, multiple, 4 reg, Q-form
1787 // ASIMD load, 1 element, all lanes, D-form, B/H/S
1788 // ASIMD load, 1 element, all lanes, D-form, D
1789 // ASIMD load, 1 element, all lanes, Q-form
1795 // ASIMD load, 2 element, multiple, D-form, B/H/S
1796 // ASIMD load, 2 element, multiple, Q-form, D
1809 // ASIMD load, 2 element, all lanes, D-form, B/H/S
1810 // ASIMD load, 2 element, all lanes, D-form, D
1811 // ASIMD load, 2 element, all lanes, Q-form
1817 // ASIMD load, 3 element, multiple, D-form, B/H/S
1818 // ASIMD load, 3 element, multiple, Q-form, B/H/S
1819 // ASIMD load, 3 element, multiple, Q-form, D
1832 // ASIMD load, 3 element, all lanes, D-form, B/H/S
1833 // ASIMD load, 3 element, all lanes, D-form, D
1834 // ASIMD load, 3 element, all lanes, Q-form, B/H/S
1835 // ASIMD load, 3 element, all lanes, Q-form, D
1841 // ASIMD load, 4 element, multiple, D-form, B/H/S
1842 // ASIMD load, 4 element, multiple, Q-form, B/H/S
1843 // ASIMD load, 4 element, multiple, Q-form, D
1856 // ASIMD load, 4 element, all lanes, D-form, B/H/S
1857 // ASIMD load, 4 element, all lanes, D-form, D
1858 // ASIMD load, 4 element, all lanes, Q-form, B/H/S
1859 // ASIMD load, 4 element, all lanes, Q-form, D
1865 //--
1867 //--
1869 // ASIMD store, 1 element, multiple, 1 reg, D-form
1870 // ASIMD store, 1 element, multiple, 1 reg, Q-form
1876 // ASIMD store, 1 element, multiple, 2 reg, D-form
1877 // ASIMD store, 1 element, multiple, 2 reg, Q-form
1883 // ASIMD store, 1 element, multiple, 3 reg, D-form
1884 // ASIMD store, 1 element, multiple, 3 reg, Q-form
1890 // ASIMD store, 1 element, multiple, 4 reg, D-form
1891 // ASIMD store, 1 element, multiple, 4 reg, Q-form
1904 // ASIMD store, 2 element, multiple, D-form, B/H/S
1905 // ASIMD store, 2 element, multiple, Q-form, B/H/S
1906 // ASIMD store, 2 element, multiple, Q-form, D
1919 // ASIMD store, 3 element, multiple, D-form, B/H/S
1920 // ASIMD store, 3 element, multiple, Q-form, B/H/S
1921 // ASIMD store, 3 element, multiple, Q-form, D
1934 // ASIMD store, 4 element, multiple, D-form, B/H/S
1935 // ASIMD store, 4 element, multiple, Q-form, B/H/S
1936 // ASIMD store, 4 element, multiple, Q-form, D