Lines Matching full:latency
11 // latency and microOps. The naming conventions is to use a prefix, one field
12 // for latency, and one or more microOp count/type designators.
14 // Latency: #cyc
21 // e.g. A57Write_6cyc_1I_6S_4V means the total latency is 6 and there are
29 def A57Write_5cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 5; }
30 def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
31 def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
32 def A57Write_5cyc_1V_FP_Forward : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
33 def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
34 def A57Write_5cyc_1W_Mul_Forward : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
35 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
36 def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
38 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
40 def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }
41 def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1; }
42 def A57Write_1cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 1; }
43 def A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2; }
44 def A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32;
46 def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35;
48 def A57Write_3cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 3; }
49 def A57Write_3cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 3; }
50 def A57Write_3cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 3; }
51 def A57Write_3cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 3; }
52 def A57Write_4cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 4; }
53 def A57Write_4cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 4; }
54 def A57Write_4cyc_1X_NonMul_Forward : SchedWriteRes<[A57UnitX]> { let Latency = 4; }
55 def A57Write_9cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 9; }
56 def A57Write_6cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 6; }
57 def A57Write_6cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 6; }
64 let Latency = 64;
70 let Latency = 6;
75 let Latency = 7;
80 let Latency = 8;
84 let Latency = 9;
88 let Latency = 8;
92 let Latency = 6;
96 let Latency = 6;
100 let Latency = 6;
104 let Latency = 6;
109 let Latency = 5;
113 let Latency = 5;
117 let Latency = 5;
121 let Latency = 5;
125 let Latency = 5;
130 let Latency = 10;
134 let Latency = 10;
139 let Latency = 1;
144 let Latency = 1;
149 let Latency = 2;
153 let Latency = 2;
157 let Latency = 2;
161 let Latency = 34;
167 let Latency = 3;
172 let Latency = 3;
177 let Latency = 3;
181 let Latency = 3;
186 let Latency = 4;
190 let Latency = 4;
199 let Latency = 10;
204 let Latency = 2;
210 let Latency = 3;
215 let Latency = 3;
219 let Latency = 3;
224 let Latency = 3;
229 let Latency = 5;
234 let Latency = 6;
238 let Latency = 6;
242 let Latency = 7;
248 let Latency = 8;
253 let Latency = 8;
257 let Latency = 8;
261 let Latency = 9;
271 let Latency = 2;
276 let Latency = 3;
281 let Latency = 3;
287 let Latency = 3;
292 let Latency = 4;
297 let Latency = 7;
302 let Latency = 5;
308 let Latency = 8;
313 let Latency = 8;
318 let Latency = 9;
323 let Latency = 9;
328 let Latency = 12;
338 let Latency = 3;
344 let Latency = 8;
350 let Latency = 4;
356 let Latency = 9;
362 let Latency = 9;
367 let Latency = 9;
372 let Latency = 9;
383 let Latency = 3;
389 let Latency = 4;
395 let Latency = 4;
400 let Latency = 6;
406 let Latency = 9;
413 let Latency = 9;
419 let Latency = 9;
430 let Latency = 10;
437 let Latency = 4;
443 let Latency = 6;
450 let Latency = 9;
456 let Latency = 12;
468 let Latency = 10;
475 let Latency = 11;
482 let Latency = 8;
495 let Latency = 8;
503 let Latency = 11;
509 let Latency = 15;
521 let Latency = 6;
534 let Latency = 6;
546 let Latency = 8;
559 let Latency = 8;