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1 //==- AArch64SchedA53.td - Cortex-A53 Scheduling Definitions -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 // ===---------------------------------------------------------------------===//
14 // The following definitions describe the simpler per-operand machine model.
17 // Cortex-A53 machine model for scheduling and other instruction cost heuristics.
19   let MicroOpBufferSize = 0; // Explicitly set to zero since A53 is in-order.
20   let IssueWidth = 2;        // 2 micro-ops are dispatched per cycle.
24   let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation
25                              // Specification - Instruction Timings"
36 //===----------------------------------------------------------------------===//
40 // Cortex-A53 is in-order.
42 def A53UnitALU    : ProcResource<2> { let BufferSize = 0; } // Int ALU
51 //===----------------------------------------------------------------------===//
52 // Subtarget-specific SchedWrite types which both map the ProcResources and
57 // ALU - Despite having a full latency of 4, most of the ALU instructions can
59 //       shift-only instruction. These latencies will be incorrect when the
65 def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 2; }
81 // Vector Load - Vector loads take 1-5 cycles to issue. For the WriteVecLd
84 //               A53WriteVLD# types represent the 1-5 cycle issues explicitly.
89                                                   let ReleaseAtCycles = [2]; }
94 def A53WriteVLD5 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 8;
97 // Pre/Post Indexing - Performed as part of address generation which is already
107 // Vector Store - Similar to vector loads, can take 1-3 cycles to issue.
109                                           let ReleaseAtCycles = [2];}
112                                                   let ReleaseAtCycles = [2]; }
148 //===----------------------------------------------------------------------===//
149 // Subtarget-specific SchedRead types.
157 // ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable
162 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
170 def A53ReadNotShifted : SchedReadAdvance<2, [WriteImm,WriteI,
184 // MAC - Operands are generally needed one cycle later in the MAC pipe.
190 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
201 //===----------------------------------------------------------------------===//
202 // Subtarget-specific InstRWs.
204 //---
206 //---
209 //---
211 //---
212 def : InstRW<[A53WriteVLD1], (instregex "LD1i(8|16|32|64)$")>;
213 def : InstRW<[A53WriteVLD1], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
214 def : InstRW<[A53WriteVLD1], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
215 def : InstRW<[A53WriteVLD2], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
216 def : InstRW<[A53WriteVLD3], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
217 def : InstRW<[A53WriteVLD4], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
218 def : InstRW<[WriteAdr, A53WriteVLD1], (instregex "LD1i(8|16|32|64)_POST$")>;
219 def : InstRW<[WriteAdr, A53WriteVLD1], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
220 def : InstRW<[WriteAdr, A53WriteVLD1], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
221 def : InstRW<[WriteAdr, A53WriteVLD2], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
222 def : InstRW<[WriteAdr, A53WriteVLD3], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
223 def : InstRW<[WriteAdr, A53WriteVLD4], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
225 def : InstRW<[A53WriteVLD1], (instregex "LD2i(8|16|32|64)$")>;
226 def : InstRW<[A53WriteVLD1], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
227 def : InstRW<[A53WriteVLD2], (instregex "LD2Twov(8b|4h|2s)$")>;
228 def : InstRW<[A53WriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
229 def : InstRW<[WriteAdr, A53WriteVLD1], (instregex "LD2i(8|16|32|64)_POST$")>;
230 def : InstRW<[WriteAdr, A53WriteVLD1], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
231 def : InstRW<[WriteAdr, A53WriteVLD2], (instregex "LD2Twov(8b|4h|2s)_POST$")>;
232 def : InstRW<[WriteAdr, A53WriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>;
234 def : InstRW<[A53WriteVLD2], (instregex "LD3i(8|16|32|64)$")>;
235 def : InstRW<[A53WriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
236 def : InstRW<[A53WriteVLD4], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)$")>;
238 def : InstRW<[WriteAdr, A53WriteVLD2], (instregex "LD3i(8|16|32|64)_POST$")>;
239 def : InstRW<[WriteAdr, A53WriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
240 def : InstRW<[WriteAdr, A53WriteVLD4], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
243 def : InstRW<[A53WriteVLD2], (instregex "LD4i(8|16|32|64)$")>;
244 def : InstRW<[A53WriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
245 def : InstRW<[A53WriteVLD5], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>;
246 def : InstRW<[A53WriteVLD4], (instregex "LD4Fourv(2d)$")>;
247 def : InstRW<[WriteAdr, A53WriteVLD2], (instregex "LD4i(8|16|32|64)_POST$")>;
248 def : InstRW<[WriteAdr, A53WriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
249 def : InstRW<[WriteAdr, A53WriteVLD5], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
250 def : InstRW<[WriteAdr, A53WriteVLD4], (instregex "LD4Fourv(2d)_POST$")>;
252 //---
254 //---
255 def : InstRW<[A53WriteVST1], (instregex "ST1i(8|16|32|64)$")>;
256 def : InstRW<[A53WriteVST1], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
257 def : InstRW<[A53WriteVST1], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
258 def : InstRW<[A53WriteVST2], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
259 def : InstRW<[A53WriteVST2], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
260 def : InstRW<[WriteAdr, A53WriteVST1], (instregex "ST1i(8|16|32|64)_POST$")>;
261 def : InstRW<[WriteAdr, A53WriteVST1], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
262 def : InstRW<[WriteAdr, A53WriteVST1], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
263 def : InstRW<[WriteAdr, A53WriteVST2], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
264 def : InstRW<[WriteAdr, A53WriteVST2], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
266 def : InstRW<[A53WriteVST1], (instregex "ST2i(8|16|32|64)$")>;
267 def : InstRW<[A53WriteVST1], (instregex "ST2Twov(8b|4h|2s)$")>;
268 def : InstRW<[A53WriteVST2], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
269 def : InstRW<[WriteAdr, A53WriteVST1], (instregex "ST2i(8|16|32|64)_POST$")>;
270 def : InstRW<[WriteAdr, A53WriteVST1], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
271 def : InstRW<[WriteAdr, A53WriteVST2], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
273 def : InstRW<[A53WriteVST2], (instregex "ST3i(8|16|32|64)$")>;
274 def : InstRW<[A53WriteVST3], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)$")>;
275 def : InstRW<[A53WriteVST2], (instregex "ST3Threev(2d)$")>;
276 def : InstRW<[WriteAdr, A53WriteVST2], (instregex "ST3i(8|16|32|64)_POST$")>;
277 def : InstRW<[WriteAdr, A53WriteVST3], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
278 def : InstRW<[WriteAdr, A53WriteVST2], (instregex "ST3Threev(2d)_POST$")>;
280 def : InstRW<[A53WriteVST2], (instregex "ST4i(8|16|32|64)$")>;
281 def : InstRW<[A53WriteVST3], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>;
282 def : InstRW<[A53WriteVST2], (instregex "ST4Fourv(2d)$")>;
283 def : InstRW<[WriteAdr, A53WriteVST2], (instregex "ST4i(8|16|32|64)_POST$")>;
284 def : InstRW<[WriteAdr, A53WriteVST3], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
285 def : InstRW<[WriteAdr, A53WriteVST2], (instregex "ST4Fourv(2d)_POST$")>;
287 //---
289 //---