Lines Matching +full:0 +full:x16
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
87 for (unsigned I = 0; I < NumXRegisters; ++I) in operator |=()
89 for (unsigned I = 0; I < NumXRegisters; ++I) in operator |=()
113 // Indexes corresponding to the forbidden x16, x17 and x30 registers are
115 reg_bitmask_t BLRThunks = 0;
116 reg_bitmask_t BLRAAZThunks = 0;
117 reg_bitmask_t BLRABZThunks = 0;
201 assert(Reg != AArch64::X16 && Reg != AArch64::X17 && Reg != AArch64::LR); in indexOfXReg()
278 // which is 31 characters (without the '\0' character).
283 return formatv("{0}{1}x{2}", CommonNamePrefix, Kind.NameInfix, N); in createThunkName()
286 return formatv("{0}{1}x{2}_x{3}", CommonNamePrefix, Kind.NameInfix, N, M); in createThunkName()
332 const ThunkKind &Kind = std::get<0>(KindAndRegs); in populateThunk()
347 assert(MF.size() == 0); in populateThunk()
356 // MOV x16, xN ; BR* instructions are not compatible with "BTI c" in populateThunk()
357 // ; branch target unless xN is x16 or x17. in populateThunk()
358 // BR* ... ; One of: BR x16 in populateThunk()
359 // ; BRA(A|B) x16, xM in populateThunk()
360 // ; BRA(A|B)Z x16 in populateThunk()
363 // MOV X16, Reg == ORR X16, XZR, Reg, LSL #0 in populateThunk()
364 BuildMI(Entry, DebugLoc(), TII->get(AArch64::ORRXrs), AArch64::X16) in populateThunk()
367 .addImm(0); in populateThunk()
369 BuildMI(Entry, DebugLoc(), TII->get(Kind.BROpcode)).addReg(AArch64::X16); in populateThunk()
409 // | MOV x16, xN | in convertBLRToBL()
410 // | BR* x16 or BR* x16, xM | in convertBLRToBL()
417 // Since linkers are allowed to clobber X16 and X17 on function calls, the in convertBLRToBL()
419 // X16 nor X17 as one of its operands. Code generation before must make sure in convertBLRToBL()
429 Register Xn = BLR.getOperand(0).getReg(); in convertBLRToBL()
481 for (unsigned OpIdx = 0; OpIdx < NumRegOperands; ++OpIdx) { in convertBLRToBL()
520 char AArch64SLSHardening::ID = 0;