Lines Matching refs:DefiningMI
186 bool processSeqRegInst(MachineInstr *DefiningMI, unsigned* StReg,
508 MachineInstr *DefiningMI; in optimizeLdStInterleave() local
521 DefiningMI = MRI->getUniqueVRegDef(SeqReg); in optimizeLdStInterleave()
523 if (!processSeqRegInst(DefiningMI, StReg, StRegKill, NumReg)) in optimizeLdStInterleave()
633 bool AArch64SIMDInstrOpt::processSeqRegInst(MachineInstr *DefiningMI, in processSeqRegInst() argument
635 assert(DefiningMI != nullptr); in processSeqRegInst()
636 if (DefiningMI->getOpcode() != AArch64::REG_SEQUENCE) in processSeqRegInst()
640 StReg[i] = DefiningMI->getOperand(2*i+1).getReg(); in processSeqRegInst()
641 StRegKill[i] = getKillRegState(DefiningMI->getOperand(2*i+1).isKill()); in processSeqRegInst()
644 if (DefiningMI->getOperand(2*i+2).isImm()) { in processSeqRegInst()
645 switch (DefiningMI->getOperand(2*i+2).getImm()) { in processSeqRegInst()