Lines Matching +full:row +full:- +full:stride
1 //=- AArch64RegisterInfo.td - Describe the AArch64 Registers -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
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63 //===----------------------------------------------------------------------===//
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147 // Floating-point control register
150 // Floating-point status register.
203 // GPR32/GPR64 but with zero-register substitution enabled.
217 // constraint used by any instructions, it is used as a common super-class.
221 // For tail calls, we can't use callee-saved registers, as they are restored
231 // branch (not call) to the "BTI c" instruction at the start of a BTI-protected
240 // This is used for pseudo-instructions that are actually implemented using a
252 // a bug in counting how many operands a Post-indexed MCInst should have which
269 let CopyCost = -1; // Don't allow copying of status registers.
275 //===----------------------------------------------------------------------===//
277 //===----------------------------------------------------------------------===//
478 // normalize 128-bit vectors to v2f64 for arg passing and such, so use
505 // Pairs, triples, and quads of 64-bit vector registers.
526 // Pairs, triples, and quads of 128-bit vector registers.
622 // 64-bit register lists with explicit type.
648 // 128-bit register lists with explicit type
737 //===----------------------------------------------------------------------===//
788 //===----- END: v8.1a atomic CASP register operands -----------------------===//
790 //===----------------------------------------------------------------------===//
795 foreach i = 0-7 in
816 //===----- END: v8.7a accelerator extension register operands -------------===//
818 // SVE predicate-as-counter registers
856 // SVE variable-size vector registers
979 // SVE predicate-as-counter operand
1026 def psub0 : SubRegIndex<16, -1>;
1027 def psub1 : SubRegIndex<16, -1>;
1088 // SVE2 multiple-of-2 multi-predicate-vector operands
1206 def zsub0 : SubRegIndex<128, -1>;
1207 def zsub1 : SubRegIndex<128, -1>;
1208 def zsub2 : SubRegIndex<128, -1>;
1209 def zsub3 : SubRegIndex<128, -1>;
1318 // SME2 multiple-of-2 or 4 multi-vector operands
1385 // SME2 strided multi-vector operands
1439 class ZPRVectorListStrided<int ElementWidth, int NumRegs, int Stride>
1444 # NumRegs # "," # Stride # "," # ElementWidth # ">";
1707 // instruction, than a property of the asm-operand itself, or its register.
1753 # !if(IsVertical, "Col", "Row") # ", "
1854 //===----------------------------------------------------------------------===//