565 static bool isPreLdStPairCandidate(MachineInstr &FirstMI, MachineInstr &MI) {  in isPreLdStPairCandidate()  argument
567   unsigned OpcA = FirstMI.getOpcode();  in isPreLdStPairCandidate()
1361 static bool areCandidatesToMergeOrPair(MachineInstr &FirstMI, MachineInstr &MI,  in areCandidatesToMergeOrPair()  argument
1369   assert(!FirstMI.hasOrderedMemoryRef() &&  in areCandidatesToMergeOrPair()
1370          !TII->isLdStPairSuppressed(FirstMI) &&  in areCandidatesToMergeOrPair()
1377   unsigned OpcA = FirstMI.getOpcode();  in areCandidatesToMergeOrPair()
1382     return !AArch64InstrInfo::isPreLdSt(FirstMI);  in areCandidatesToMergeOrPair()
1385   if (AArch64InstrInfo::isPreLdSt(FirstMI) && AArch64InstrInfo::isPreLdSt(MI))  in areCandidatesToMergeOrPair()
1412   if (isPreLdStPairCandidate(FirstMI, MI))  in areCandidatesToMergeOrPair()
1455 canRenameUpToDef(MachineInstr &FirstMI, LiveRegUnits &UsedInBetween,  in canRenameUpToDef()  argument
1458   if (!FirstMI.mayStore())  in canRenameUpToDef()
1464   auto RegToRename = getLdStRegOp(FirstMI).getReg();  in canRenameUpToDef()
1466   if (!getLdStRegOp(FirstMI).isKill() &&  in canRenameUpToDef()
1467       !any_of(FirstMI.operands(),  in canRenameUpToDef()
1473     LLVM_DEBUG(dbgs() << "  Operand not killed at " << FirstMI);  in canRenameUpToDef()
1540   if (!forAllMIsUntilDef(FirstMI, RegToRename, TRI, LdStLimit, CheckMIs))  in canRenameUpToDef()
1648     std::optional<bool> MaybeCanRename, MachineInstr &FirstMI, MachineInstr &MI,  in findRenameRegForSameLdStRegPair()  argument
1656   auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg());  in findRenameRegForSameLdStRegPair()
1657   MachineFunction &MF = *FirstMI.getParent()->getParent();  in findRenameRegForSameLdStRegPair()
1661   const bool IsLoad = FirstMI.mayLoad();  in findRenameRegForSameLdStRegPair()
1665       MaybeCanRename = {canRenameUntilSecondLoad(FirstMI, MI, UsedInBetween,  in findRenameRegForSameLdStRegPair()
1669           canRenameUpToDef(FirstMI, UsedInBetween, RequiredClasses, TRI)};  in findRenameRegForSameLdStRegPair()
1688   MachineInstr &FirstMI = *I;  in findMatchingInsn()  local
1691   bool MayLoad = FirstMI.mayLoad();  in findMatchingInsn()
1692   bool IsUnscaled = TII->hasUnscaledLdStOffset(FirstMI);  in findMatchingInsn()
1693   Register Reg = getLdStRegOp(FirstMI).getReg();  in findMatchingInsn()
1694   Register BaseReg = AArch64InstrInfo::getLdStBaseOp(FirstMI).getReg();  in findMatchingInsn()
1695   int Offset = AArch64InstrInfo::getLdStOffsetOp(FirstMI).getImm();  in findMatchingInsn()
1696   int OffsetStride = IsUnscaled ? TII->getMemScale(FirstMI) : 1;  in findMatchingInsn()
1697   bool IsPromotableZeroStore = isPromotableZeroStoreInst(FirstMI);  in findMatchingInsn()
1717   LLVM_DEBUG(dbgs() << "Find match for: "; FirstMI.dump());  in findMatchingInsn()
1731     if (areCandidatesToMergeOrPair(FirstMI, MI, Flags, TII) &&  in findMatchingInsn()
1763       bool IsPreLdSt = isPreLdStPairCandidate(FirstMI, MI);  in findMatchingInsn()
1872                 findRenameRegForSameLdStRegPair(MaybeCanRename, FirstMI, MI,  in findMatchingInsn()
1897             MayLoad && !UsedRegUnits.available(getLdStRegOp(FirstMI).getReg()));  in findMatchingInsn()
1900                           << "Reg '" << getLdStRegOp(FirstMI)  in findMatchingInsn()
1904         if (RtNotModified && !mayAlias(FirstMI, MemInsns, AA)) {  in findMatchingInsn()
1905           if (ModifiedRegUnits.available(getLdStRegOp(FirstMI).getReg())) {  in findMatchingInsn()
1912               MaybeCanRename, FirstMI, MI, Reg, DefinedInBB, UsedInBetween,  in findMatchingInsn()