Lines Matching refs:b11

1253   let CRm{1-0}   = 0b11;
1347 let Inst{11-10} = 0b11;
1454 def RAX1 : CryptoRRR_2D<0b0,0b11, "rax1">;
1523 def SM3TT2B : CryptoRRRi2Tied<0b0, 0b11, "sm3tt2b">;
1562 def LDAPRX : RCPCLoad<0b11, "ldapr", GPR64>;
1727 def DB : SignAuthOneData<prefix, 0b11, !strconcat(asm, "db"), op>;
1731 def DZB : SignAuthZero<prefix_z, 0b11, !strconcat(asm, "dzb"), op>;
1959 def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32,
2112 defm MOVK : InsertImmediate<0b11, "movk">;
2389 defm RORV : Shift<0b11, "ror", rotr>;
2536 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">;
2541 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
2655 defm STZ2G : MemTagStore<0b11, "stz2g">;
2722 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
2737 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
2738 defm BICS : LogicalRegS<0b11, 1, "bics",
3206 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">, Requires<[HasEL3]>;
3210 def SMC : ExceptionGeneration<0b000, 0b11, "smc">, Requires<[HasEL3]>;
3280 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
3287 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64Op, "ldr", f64, load>;
3288 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128Op, "ldr", f128, load>;
3292 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;
3296 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
3303 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;
3453 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64z, uimm12s8, "ldr",
3469 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64Op, uimm12s8, "ldr",
3472 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128Op, uimm12s16, "ldr",
3598 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",
3608 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
3628 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
3672 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
3677 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64z, "ldur",
3693 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64Op, "ldur",
3696 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128Op, "ldur",
3842 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",
3852 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
3934 defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
3940 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
3947 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
3951 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
3960 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64z, "ldr">;
3965 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64Op, "ldr">;
3966 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128Op, "ldr">;
3970 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32z, "ldrsh">;
3974 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32z, "ldrsb">;
3987 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64z, "ldr">;
3992 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64Op, "ldr">;
3993 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128Op, "ldr">;
3997 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32z, "ldrsh">;
4001 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32z, "ldrsb">;
4066 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
4074 defm STRD : Store64RO<0b11, 1, 0b00, FPR64Op, "str", f64, store>;
4179 defm STRX : StoreUIz<0b11, 0, 0b00, GPR64z, uimm12s8, "str",
4195 defm STRD : StoreUI<0b11, 1, 0b00, FPR64Op, uimm12s8, "str",
4315 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64z, "stur",
4331 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64Op, "stur",
4356 defm STLURX : BaseStoreUnscaleV84<"stlur", 0b11, 0b00, GPR64>;
4358 defm LDAPURSBW : BaseLoadUnscaleV84<"ldapursb", 0b00, 0b11, GPR32>;
4361 defm LDAPURSHW : BaseLoadUnscaleV84<"ldapursh", 0b01, 0b11, GPR32>;
4365 defm LDAPURX : BaseLoadUnscaleV84<"ldapur", 0b11, 0b01, GPR64>;
4487 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
4495 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64z, "str", pre_store, i64>;
4500 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64Op, "str", pre_store, f64>;
4551 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64z, "str", post_store, i64>;
4556 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64Op, "str", post_store, f64>;
4616 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
4621 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
4626 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
4631 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
4651 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
4656 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
4661 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
4664 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
4667 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
4670 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
4675 def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">;
4681 def STLLRX : StoreRelease <0b11, 1, 0, 0, 0, GPR64, "stllr">;
4704 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", any_fp_to_sint>;
4705 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;
4706 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", any_fp_to_sint>;
4707 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;
4951 defm FRINT64X : FRIntNNT<0b11, "frint64x", int_aarch64_frint64x>;
5602 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
5612 defm BIF : SIMDLogicalThreeVectorTied<1, 0b11, "bif">;
7488 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
7490 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;
9963 let Inst{4-3} = 0b11;
9986 def SWPPAL : LSE128Base<0b000, 0b11, 0b1, "swppal">;
9990 def LDCLRPAL : LSE128Base<0b001, 0b11, 0b0, "ldclrpal">;
9994 def LDSETPAL : LSE128Base<0b011, 0b11, 0b0, "ldsetpal">;
10005 …def STILPXpre: BaseLRCPC3IntegerLoadStorePair<0b11, 0b00, 0b0000, (outs GPR64sp:$wback), (ins GP…
10007 …def STILPX: BaseLRCPC3IntegerLoadStorePair<0b11, 0b00, 0b0001, (outs), (ins GPR64:$Rt, GPR64:…
10009 …def LDIAPPXpost: BaseLRCPC3IntegerLoadStorePair<0b11, 0b01, 0b0000, (outs GPR64sp:$wback, GPR64:$R…
10011 …def LDIAPPX: BaseLRCPC3IntegerLoadStorePair<0b11, 0b01, 0b0001, (outs GPR64:$Rt, GPR64:$Rt2), …
10022 …def STLRXpre: BaseLRCPC3IntegerLoadStore<0b11, 0b10, (outs GPR64sp:$wback), (ins GPR6…
10023 …def LDAPRWpost: BaseLRCPC3IntegerLoadStore<0b10, 0b11, (outs GPR64sp:$wback, GPR32:$Rt), (ins GPR6…
10024 …def LDAPRXpost: BaseLRCPC3IntegerLoadStore<0b11, 0b11, (outs GPR64sp:$wback, GPR64:$Rt), (ins GPR6…
10032 …defm STLURd: LRCPC3NEONLoadStoreUnscaledOffset<0b11, 0b00, FPR64 , (outs), (ins FPR64 :$Rt, GPR64…
10037 …defm LDAPURd: LRCPC3NEONLoadStoreUnscaledOffset<0b11, 0b01, FPR64 , (outs FPR64 :$Rt), (ins GPR64s…
10038 …defm LDAPURq: LRCPC3NEONLoadStoreUnscaledOffset<0b00, 0b11, FPR128, (outs FPR128:$Rt), (ins GPR64s…
10128 defm BF2CVTL : SIMDMixedTwoVectorFP8<0b11, "bf2cvtl">;