Lines Matching +full:in +full:- +full:masks

1 //=----- AArch64InstrGISel.td - AArch64 GISel target pseudos -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
28 // Pseudo for a rev16 instruction. Produced post-legalization from
29 // G_SHUFFLE_VECTORs with appropriate masks.
36 // Pseudo for a rev32 instruction. Produced post-legalization from
37 // G_SHUFFLE_VECTORs with appropriate masks.
44 // Pseudo for a rev64 instruction. Produced post-legalization from
45 // G_SHUFFLE_VECTORs with appropriate masks.
52 // Represents an uzp1 instruction. Produced post-legalization from
53 // G_SHUFFLE_VECTORs with appropriate masks.
60 // Represents an uzp2 instruction. Produced post-legalization from
61 // G_SHUFFLE_VECTORs with appropriate masks.
68 // Represents a zip1 instruction. Produced post-legalization from
69 // G_SHUFFLE_VECTORs with appropriate masks.
76 // Represents a zip2 instruction. Produced post-legalization from
77 // G_SHUFFLE_VECTORs with appropriate masks.
84 // Represents a dup instruction. Produced post-legalization from
85 // G_SHUFFLE_VECTORs with appropriate masks.
114 // Represents a trn1 instruction. Produced post-legalization from
115 // G_SHUFFLE_VECTORs with appropriate masks.
122 // Represents a trn2 instruction. Produced post-legalization from
123 // G_SHUFFLE_VECTORs with appropriate masks.
130 // Represents an ext instruction. Produced post-legalization from
131 // G_SHUFFLE_VECTORs with appropriate masks.
327 let Predicates = [HasNEON] in {
348 let Predicates = [HasNoLSE] in {
367 let GIIgnoreCopies = 1 in
462 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
547 let AddedComplexity = 19 in {