Lines Matching refs:b10
3094 let Inst{23-22} = 0b10;
3395 let Inst{11-10} = 0b10;
3851 let Inst{11-10} = 0b10;
3929 let Inst{11-10} = 0b10;
4001 let Inst{11-10} = 0b10;
4073 let Inst{11-10} = 0b10;
4145 let Inst{11-10} = 0b10;
4215 let Inst{11-10} = 0b10;
4372 let Inst{11-10} = 0b10;
4861 BaseMemTagStore<opc1, 0b10, insn, "\t$Rt, [$Rn, $offset]", "",
5430 let Inst{11-10} = 0b10;
5970 def v4f16 : BaseSIMDThreeSameVector<0, U, {S,0b10}, {0b00,opc}, V64,
5973 def v8f16 : BaseSIMDThreeSameVector<1, U, {S,0b10}, {0b00,opc}, V128,
5993 def v4f16 : BaseSIMDThreeSameVector<0, U, {S,0b10}, {0b00,opc}, V64,
5996 def v8f16 : BaseSIMDThreeSameVector<1, U, {S,0b10}, {0b00,opc}, V128,
6015 def v4f16 : BaseSIMDThreeSameVectorTied<0, U, {S,0b10}, {0b00,opc}, V64,
6019 def v8f16 : BaseSIMDThreeSameVectorTied<1, U, {S,0b10}, {0b00,opc}, V128,
6135 def v8i8 : BaseSIMDThreeSameVectorDot<0, U, 0b10, {0b001, Mixed}, asm, ".2s", ".8b", V64,
6137 def v16i8 : BaseSIMDThreeSameVectorDot<1, U, 0b10, {0b001, Mixed}, asm, ".4s", ".16b", V128,
6257 let Inst{11-10} = 0b10;
6282 let Inst{11-10} = 0b10;
6302 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, 0b00, V64,
6305 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, 0b00, V128,
6338 def v2i32 : BaseSIMDVectorLShiftLongBySize<0, 0b10, V64,
6340 def v4i32 : BaseSIMDVectorLShiftLongBySize<1, 0b10, V128,
6360 def v2i32_v1i64 : BaseSIMDTwoSameVector<0, U, 0b10, opc, 0b00, V64,
6363 def v4i32_v2i64 : BaseSIMDTwoSameVector<1, U, 0b10, opc, 0b00, V128,
6386 def v2i32_v1i64 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, 0b00, V64,
6390 def v4i32_v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, 0b00, V128,
6411 def v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, 0b00, V64,
6414 def v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, 0b00, V128,
6436 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, 0b00, V64,
6439 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, 0b00, V128,
6600 let Inst{11-10} = 0b10;
6623 let Inst{11-10} = 0b10;
6640 def v2i32 : BaseSIMDMixedTwoVector<0, U, 0b10, opc, V128, V64,
6643 def v4i32 : BaseSIMDMixedTwoVectorTied<1, U, 0b10, opc, V128, V128,
6687 let Inst{11-10} = 0b10;
6707 def v2i32rz : BaseSIMDCmpTwoVector<0, U, 0b10, 0b00, opc, V64,
6710 def v4i32rz : BaseSIMDCmpTwoVector<1, U, 0b10, 0b00, opc, V128,
6785 let Inst{11-10} = 0b10;
6807 let Inst{11-10} = 0b10;
7275 let Inst{11-10} = 0b10;
7387 def v1i32: BaseSIMDThreeScalarTied<U, 0b10, R, opc, (outs FPR32:$dst),
7406 def NAME#16 : BaseSIMDThreeScalar<U, {S,0b10}, {0b00,opc}, FPR16, asm,
7423 def NAME#16 : BaseSIMDThreeScalar<U, {S,0b10}, {0b00,opc}, FPR16, asm,
7458 def i32 : BaseSIMDThreeScalarMixed<U, 0b10, opc,
7471 def i32 : BaseSIMDThreeScalarMixed<U, 0b10, opc,
7500 let Inst{11-10} = 0b10;
7520 let Inst{11-10} = 0b10;
7542 let Inst{11-10} = 0b10;
7556 let Inst{11-10} = 0b10;
7635 def v1i32 : BaseSIMDTwoScalar<U, 0b10, 0b00, opc, FPR32, FPR32, asm,
7650 def v1i32 : BaseSIMDTwoScalarTied<U, 0b10, opc, FPR32, FPR32, asm,
7665 def v1i32 : BaseSIMDTwoScalar<U, 0b10, 0b00, opc, FPR32, FPR64, asm,
7690 let Inst{11-10} = 0b10;
7732 let Inst{11-10} = 0b10;
7747 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR32, V128,
7760 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR64, V128,
7847 let Inst{17-16} = 0b10;
7914 let Inst{17-16} = 0b10;
7919 let Inst{17-16} = 0b10;
7959 let Inst{17-16} = 0b10;
8025 let Inst{17-16} = 0b10;
8049 let Inst{17-16} = 0b10;
8148 def v8i8Three : BaseSIMDTableLookup<0, 0b10, op, V64, VecListThree16b,
8156 def v16i8Three: BaseSIMDTableLookup<1, 0b10, op, V128, VecListThree16b,
8192 def v8i8Three : BaseSIMDTableLookupTied<0, 0b10, op, V64, VecListThree16b,
8200 def v16i8Three: BaseSIMDTableLookupTied<1, 0b10, op, V128, VecListThree16b,
8259 …def v16f8 : BaseSIMDTableLookupIndexed<0b1, {0b10,?,?,0b1}, V128, VecListOne16b, VectorIndexS, asm…
8270 …def v16f8 : BaseSIMDTableLookupIndexed<0b1, {0b01,?,0b10}, V128, VecListOne16b, VectorIndexD, asm,…
8314 let Inst{17-16} = 0b10;
8680 : BaseSIMDMixedTwoVector<0, 0, 0b10, 0b10110, V128, V128,
8687 : BaseSIMDMixedTwoVectorTied<1, 0, 0b10, 0b10110, V128, V128,
8801 def v4f16 : BaseSIMDThreeSameVectorIndexH<0, U, 0b10, opc, asm, ".2s", ".2h", ".h",
8803 def v8f16 : BaseSIMDThreeSameVectorIndexH<1, U, 0b10, opc, asm, ".4s", ".4h", ".h",
8848 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
8860 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
8899 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
9046 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc, V64, V64,
9054 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
9083 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
9185 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
9197 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
9218 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
9259 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
9271 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
9311 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
9323 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
9365 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
9377 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
9398 def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
9440 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
9454 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
9502 def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
9548 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
9560 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
9604 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
9616 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
10443 def v4s : BaseSIMDLdSt<1, 1, opcode, 0b10, asm,
10455 def v2s : BaseSIMDLdSt<0, 1, opcode, 0b10, asm,
10470 def v4s_POST : BaseSIMDLdStPost<1, 1, opcode, 0b10, asm,
10490 def v2s_POST : BaseSIMDLdStPost<0, 1, opcode, 0b10, asm,
10516 def v4s : BaseSIMDLdSt<1, 0, opcode, 0b10, asm, (outs),
10528 def v2s : BaseSIMDLdSt<0, 0, opcode, 0b10, asm, (outs),
10542 def v4s_POST : BaseSIMDLdStPost<1, 0, opcode, 0b10, asm,
10562 def v2s_POST : BaseSIMDLdStPost<0, 0, opcode, 0b10, asm,
10770 def v2s : BaseSIMDLdR<0, R, opcode, S, 0b10, asm,
10772 def v4s : BaseSIMDLdR<1, R, opcode, S, 0b10, asm,
10791 def v2s_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b10, asm,
10794 def v4s_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b10, asm,
11217 def v2i32 : BaseSIMDThreeSameVectorTiedR0<0, U, 0b10, opc, V64, asm, ".2s",
11220 def v4i32 : BaseSIMDThreeSameVectorTiedR0<1, U, 0b10, opc, V128, asm, ".4s",
11253 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
11264 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
11286 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
11372 def v2f32 : BaseSIMDThreeSameVectorComplex<0, U, 0b10, opcode, V64, rottype,
11379 def v4f32 : BaseSIMDThreeSameVectorComplex<1, U, 0b10, opcode, V128, rottype,
11444 def v2f32 : BaseSIMDThreeSameVectorTiedComplex<0, U, 0b10, opcode, V64,
11451 def v4f32 : BaseSIMDThreeSameVectorTiedComplex<1, U, 0b10, opcode, V128,
11528 def v4f32_indexed : BaseSIMDIndexedTiedComplex<1, 1, 0, 0b10, opc1, opc2,
11551 let Inst{11-10} = 0b10;
11617 let Inst{11-10} = 0b10;
11797 let Sz = 0b10, Acq = Acq, Rel = Rel in def W : BaseCAS<order, "", GPR32>;
11845 let Sz = 0b10, Acq = Acq, Rel = Rel in def W : BaseSWP<order, "", GPR32>;
11881 let Sz = 0b10, Acq = Acq, Rel = Rel, opc = opc in
12088 def RN : MOPSMemoryCopy<opcode, 0b00, 0b10, asm # "rn">;
12092 def WTRN : MOPSMemoryCopy<opcode, 0b01, 0b10, asm # "wtrn">;
12094 def RT : MOPSMemoryCopy<opcode, 0b10, 0b00, asm # "rt">;
12095 def RTWN : MOPSMemoryCopy<opcode, 0b10, 0b01, asm # "rtwn">;
12096 def RTRN : MOPSMemoryCopy<opcode, 0b10, 0b10, asm # "rtrn">;
12097 def RTN : MOPSMemoryCopy<opcode, 0b10, 0b11, asm # "rtn">;
12100 def TRN : MOPSMemoryCopy<opcode, 0b11, 0b10, asm # "trn">;
12107 def RN : MOPSMemoryMove<opcode, 0b00, 0b10, asm # "rn">;
12111 def WTRN : MOPSMemoryMove<opcode, 0b01, 0b10, asm # "wtrn">;
12113 def RT : MOPSMemoryMove<opcode, 0b10, 0b00, asm # "rt">;
12114 def RTWN : MOPSMemoryMove<opcode, 0b10, 0b01, asm # "rtwn">;
12115 def RTRN : MOPSMemoryMove<opcode, 0b10, 0b10, asm # "rtrn">;
12116 def RTN : MOPSMemoryMove<opcode, 0b10, 0b11, asm # "rtn">;
12119 def TRN : MOPSMemoryMove<opcode, 0b11, 0b10, asm # "trn">;
12220 let Inst{11-10} = 0b10;